Semiconductor storage device

A semiconductor storage device, comprising:

• a memory cell array comprising a plurality of memory blocks comprising a plurality of memory strings, each of the memory blocks being divided into first and second sub-blocks, and each of the memory strings being divided into first and second portions corresponding to the first and second sub-blocks, respectively, each memory string including, in the first portion, a first select transistor and a second select transistor connected in series and, in the second portion, a third select transistor and a fourth transistor connected in series, and a plurality of memory transistors connected in series between the second and third select transistors;
• a row decoder configured to independently apply voltages to the first, second, third, and fourth select transistors in each memory string;
• and
• a sequencer configured to perform a first mode data erase operation for erasing an entire memory block including the memory string and a second mode data erase operation to erase one of the first or second sub-blocks in a memory block, wherein
• the sequencer has a first mode for erasing the first and second memory cells at the same time in the data erase operation and a second mode for erasing just one of first and second memory cells in the data erase operation, and
• in the first mode:
• a first voltage is applied to a bit line connected to a memory string in a memory block and a source line connected to the memory string,
• a second voltage lower than the first voltage is applied to a first select gate line connected to a gate of the first select transistor in the memory string,
• a third voltage is applied to a second select gate line connected to a gate of the second select transistor in the memory string,
• a fourth voltage is applied to a third select gate line connected to a gate of third select transistor in the memory string,
• a fifth voltage lower than the first voltage is applied to a fourth select gate line connected to a gate of the fourth select transistor in the memory string, and
• a sixth voltage lower than the first, second, third, fourth and fifth voltages is applied to word lines connected to gates of memory cell transistors in the first portion of the memory string and word lines connected to gates of memory cell transistors in the second portion of the memory string.

A memory cell array, comprising:

• a semiconductor substrate;
• a plurality of memory strings on the semiconductor substrate, each of the memory strings comprising first, second, third and fourth select transistors and first and second memory cells connected in series with each other in a first direction perpendicular to a surface of the semiconductor substrate, the first and fourth select transistors being at respective ends of the series connection;
• first, second, third and fourth select gate lines connected to gates of the first, second, third and fourth select transistors, respectively;
• first and second word lines connected to gates of the first and second memory cells, respectively;
• a bit line connected to the first select transistor;
• and
• a source line connected to the fourth select transistor, wherein
• in a first mode of a data erase operation to erase both the first and second memory cells,
• the bit line and the source line receive a first voltage higher than a power supply voltage;
• the first select gate line receives a second voltage higher than the power supply voltage and lower than the first voltage;
• the second select gate line receives a third voltage equal to the first voltage;
• the third select gate line receives a fourth voltage equal to the first voltage;
• the fourth select gate line receives a fifth voltage lower than the first voltage;
• and
• the first and second word lines receive a sixth voltage lower than the first, second, third, fourth and fifth voltages.