Semiconductor memory device
AssigneeSK hynix Inc.
InventorTae Heui Kwon
Life of this patent
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Abstract
A semiconductor memory apparatus may include a cell string and a page buffer. The cell string may include a drain select transistor coupled with a bit line, and memory cells coupled with the drain select transistor. The page buffer may be coupled to the cell string through the bit line. The page buffer may include a latch and a first current path. The latch may store data of a value indicative of a result of a threshold voltage verification on the drain select transistor. The first current path may set a voltage of the bit line to a program inhibit voltage, based on the value of the data stored in the latch.
Claims18
A semiconductor memory apparatus comprising:
- a cell string including a drain select transistor coupled with a bit line, and memory cells coupled with the drain select transistor;
- and
- a page buffer coupled to the cell string through the bit line,
- wherein the page buffer comprises:
- a latch configured to store data of a value indicative of a result of a threshold voltage verification on the drain select transistor;
- and
- a first current path configured to set a voltage of the bit line to a program inhibit voltage based on the value of the data stored in the latch,
- wherein the first current path comprises:
- a bit line select transistor coupled to the bit line;
- a page buffer sensing transistor coupled between the bit line select transistor and a first node;
- and
- a power supply transistor coupled between a power supply and the first node and configured to transmit a voltage of the power supply to the first node based on the data of the first value stored in the latch.
A semiconductor memory apparatus comprising:
- a cell string including a drain select transistor, and memory cells coupled with the drain select transistor;
- a latch configured to store data of a value indicative of a result of a threshold voltage verification on the drain select transistor;
- a bit line select transistor coupled to the drain select transistor;
- a page buffer sensing transistor coupled between the bit line select transistor and a first node;
- a power supply transistor coupled between a power supply and the first node;
- and
- a voltage select circuit configured to supply a voltage of the power supply,
- wherein the power supply transistor is selectively turned on based on the value of the data stored in the latch so that the voltage of the power supply is supplied to the bit line as a program inhibit voltage.
Dependencies are inferred from the claim text.