US 11,386,954 B2Granted

Memory device and method for operating the same including setting a recovery voltage

AssigneeMicron Technology, Inc.

InventorsMarco Sforzin, Paolo Amato, Innocenzo Tortorelli

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Abstract

A memory device can include a plurality of memory cells including a first group of memory cells and a second group of memory cells programmed to a predefined logic state. The plurality of memory cells includes a memory controller configured to apply a reading voltage to at least one selected memory cell of the first group during a reading operation, apply the reading voltage to the memory cells of the second group, and responsive to the logic state of at least one memory cell of the second group being assessed to be different from the predefined logic state perform a refresh operation of the memory cells of the first group by applying a recovery voltage higher than the reading voltage to assess the logic state thereof and reprogramming the memory cells of the first group to the logic state assessed with the recovery voltage.

Claims17

Dependent claims

A memory device, comprising:

a plurality of memory cells arranged in at least one array of memory cells, each of the plurality of memory cells programmable to at least two logic states, each logic state corresponding to a respective nominal electric resistance value of the memory cell, wherein the plurality of memory cells comprises:
a first group of memory cells;
and
a second group of memory cells programmed to a predefined logic state of the at least two logic states;
a memory controller coupled to the plurality of memory cells and configured to:
apply a reading voltage to at least one selected memory cell of the first group during a reading operation to assess the logic state thereof, wherein the logic state assessment comprises:
biasing a corresponding bit line to a voltage corresponding to the reading voltage, biasing a corresponding word line to a word line selection voltage lower than the reading voltage, and biasing other word lines to a first deselection voltage intermediate between the word line selection voltage and the bit line reading voltage;
apply the reading voltage to the memory cells of the second group to assess the logic state thereof;
and
responsive to the logic state of at least one memory cell of the second group being assessed to be different from the predefined logic state, perform a refresh operation of the memory cells of the first group by:
applying a recovery voltage higher than the reading voltage to assess the logic state thereof;
and
reprogramming the memory cells of the first group to the logic state assessed with the recovery voltage;
carrying out, using the memory controller, a recovery voltage setting operation to set the recovery voltage, the recovery voltage setting operation comprising:
setting an initial test voltage;
applying a test voltage to the memory cells of the second group to assess the logic state thereof;
responsive to the logic state of at least one memory cell of the second group assessed with the test voltage being different from the predefined logic state:
increasing the value of the test voltage;
and
repeating application of the test voltage to the memory cells of the second group to assess the logic state thereof using the increased value of the test voltage;
and
responsive to the logic state of all the memory cells of the second group assessed with the test voltage being equal to the predefined logic state, the memory controller setting the recovery voltage according to the test voltage used in the last application of the test voltage to the memory cells of the second group to assess the logic state thereof that has been carried out.

19 more elements

A method for operating a memory device, comprising:

applying a reading voltage to a first group and a second group of memory cells of a memory component;
and
responsive to a logic state of at least one memory cell of the second group assessed as different from a predefined logic state, performing a refresh operation of the memory cells of the first group by applying a recovery voltage higher than the reading voltage to assess the logic state thereof;
reprogramming the memory cells of the first group to the logic state assessed with the recovery voltage;
carrying out a recovery voltage setting operation to set the recovery voltage, the recovery voltage setting operation comprising:
setting an initial test voltage such that it corresponds to the reading voltage;
applying a test voltage to the memory cells of the second group to assess the logic state thereof;
responsive to the logic state of at least one memory cell of the second group assessed with the test voltage being different from the predefined logic state:
increasing the value of the test voltage;
and
repeating application of the test voltage to the memory cells of the second group to assess the logic state thereof using the increased value of the test voltage;
responsive to the logic state of all the memory cells of the second group assessed with the test voltage being equal to the predefined logic state, setting the recovery voltage according to the test voltage used in the last application of the test voltage to the memory cells of the second group to assess the logic state thereof that has been carried out.

9 more elements

A method for operating a memory device, comprising:

programming memory cells of a second group of a plurality of memory cells of the memory device to a predefined logic state of at least two logic states, each logic state corresponding to a respective nominal electric resistance value of the each of the memory cells of the second group;
during a reading operation, applying a reading voltage to at least one selected memory cell of a first group of memory cells of the plurality of memory cells to assess a logic state thereof;
applying the reading voltage to the memory cells of the second group to assess the logic state thereof;
responsive to the logic state of at least one memory cell of the second group assessed as different from the predefined logic state:
performing a refresh operation of the memory cells of the first group by applying a recovery voltage higher than the reading voltage to assess the logic state thereof;
and
reprogramming the memory cells of the first group to the logic state assessed with the recovery voltage;
carrying out a recovery voltage setting operation to set the recovery voltage, the recovery voltage setting operation comprising:
setting an initial test voltage;
applying a test voltage to the memory cells of the second group to assess the logic state thereof;
responsive to the logic state of at least one memory cell of the second group assessed with the test voltage being different from the predefined logic state:
increasing the value of the test voltage;
and
repeating application of the test voltage to the memory cells of the second group to assess the logic state thereof using the increased value of the test voltage;
and
responsive to the logic state of all the memory cells of the second group assessed with the test voltage being equal to the predefined logic state, setting the recovery voltage according to the test voltage used in the last application of the test voltage to the memory cells of the second group to assess the logic state thereof that has been carried out.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/959,556Filed 3 Dec 2019
Published: US 2021/0407592 A130 Dec 2021
Granted: 12 Jul 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

G11C 13/0033
Auxiliary circuits: disturbance prevention or evaluation; Refreshing of disturbed memory data
G11C 13/0004
Using resistive RAM [RRAM] elements: comprising amorphous/crystalline phase transition cells
G11C 13/0026
Address circuits or decoders: bit-line or column circuits
G11C 13/0038
Auxiliary circuits: power supply circuits