Stacked DRAM memory device for improving integration density and reducing bit line capacitance
AssigneeSK hynix Inc.
InventorKee Teok Park
Life of this patent
Estimating the term…
Abstract
A stacked memory device includes a plurality of lower word lines extending in a first direction, a bit line positioned over the plurality of the lower word lines and extending in a second direction intersecting with the first direction, and a plurality of upper word lines positioned over the bit line and extending in the first direction. The stacked memory device also includes a plurality of lower memory cells including a lower capacitor and a lower switching element between the lower word lines and the bit line. The stacked memory device further includes a plurality of upper memory cells including an upper capacitor and an upper switching element between the bit line and the upper word lines.
Claims20
A stacked memory device comprising:
- a plurality of lower word lines extending in a first direction;
- a bit line positioned over the plurality of the lower word lines and extending in a second direction intersecting with the first direction;
- a plurality of upper word lines stacked over the bit line and extending in the first direction;
- a plurality of lower memory cells electrically connected between the plurality of lower word lines and the bit line;
- and
- a plurality of upper memory cells electrically connected between the plurality of upper word lines and the bit line,
- wherein each of the plurality of lower and upper memory cells includes a transistor with a gate connected to one of the lower and upper word lines and a capacitor connected to the transistor, and
- wherein at least one transistor of the lower and upper memory cells is configured to have a first distance between the bit line and its gate and another transistor is configured to have a second distance between the bit line and gate of the another transistor, and the first distance is different from the second distance.
A stacked memory device comprising:
- a first memory array layer;
- and
- a second memory array layer stacked on the first memory array layer along a vertical direction,
- wherein each of the first and second memory array layers includes a bit line, a plurality of lower memory cells arranged under the bit line, and a plurality of upper memory cells arranged over the bit line,
- wherein each of the plurality of lower memory cells and the plurality of upper memory cells includes a transistor with a drain, a source and a gate, and a capacitor connected to the transistor, and
- wherein a first transistor of the lower memory cells of at least one of first and second memory array layers includes a first drain length and a second transistor of the lower memory cells of at least one of the first and second memory array layers includes a second drain length different from the first drain length.
A stack memory device, comprising:
- a first word line extending to a first direction;
- a first bit line stacked over the first word line, extending a second direction perpendicular to the first direction;
- a second word line stacked over the first bit line to overlap the first word line;
- a first memory cell including a first switching transistor and a first capacitor, the first switching transistor with a first gate electrically connected to the first word line, a first drain electrically connected to the first bit line, and a first source electrically connected to the first capacitor;
- and
- a second memory cell including a second switching transistor and a second capacitor, the second switching transistor with a second gate electrically connected to the second word line, a second drain electrically connected to the first bit line, and a second source electrically connected to the second capacitor,
- wherein a length of the first drain is different from a length of the second drain.
Dependencies are inferred from the claim text.