Apparatuses, systems, and methods for latch reset logic

A method comprising:

• storing stored data in a local latch responsive to a first clock signal or a second clock signal at an active level, wherein the stored data is associated with a first memory bank or a second memory bank;
• resetting the stored data responsive to a combined reset signal at an active level;
• providing the combined reset signal at an active level based on an activation of a first reset signal associated with the first memory bank and a second reset signal associated with the second memory bank;
• and
• inactivating the combined reset signal when the first clock signal or the second clock signal rises to the active level.

An apparatus comprising:

• a first latch circuit configured to receive a first access signal and a first clock signal and provide a first inverse reset signal based on the first access signal and the first clock signal, wherein the first inverse reset signal is at an active level when the first clock signal is active;
• a second latch circuit configured to receive a second access signal and a second clock signal and provide a second inverse reset signal based on the second access signal and the second clock signal, wherein the second inverse reset signal is at an active level when the second clock signal is active;
• and
• a logic circuit configured to provide a combined reset signal at an active level when both the first inverse reset signal and the second inverse reset signal are at the inactive level;
• and
• a local latch configured to store data and reset the stored data responsive to the combined reset signal at the active level.