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US 11,386,948 B1Granted
Multiplexors under an array of memory cells
AssigneeMicron Technology, Inc.
InventorsYuan He, Tae H. Kim
Life of this patent
Estimating the term…
Abstract
A sense amplifier can be formed outside of/horizontally adjacent to an array of vertically stacked tiers of memory cells. Memory cells can be sensed via multiplexors formed under the array that can operate to couple vertical sense lines (to which the memory cells are coupled) to horizontal sense lines (to which the sense amplifier is coupled).
Claims19
A memory device, comprising:
- an array of memory cells comprising:
- a plurality of vertically stacked tiers of memory cells;
- and
- a respective plurality of horizontal access lines coupled to each of the plurality of tiers;
- a plurality vertical sense lines coupled to each of the plurality of tiers;
- semiconductor under the array circuitry, comprising a plurality of multiplexors each coupled to a respective vertical sense line and to a respective horizontal sense line;
- and
- a plurality of sense amplifiers each coupled to a respective pair of horizontal sense lines;
- wherein each of the plurality of multiplexors comprises a respective pair of transistors;
- and
- wherein the respective pair of transistors is configured such that:
- activation of a first of the respective pair of transistors causes the respective vertical sense line to be electrically coupled to the respective horizontal sense line;
- and
- activation of a second of the respective pair of transistors causes the respective vertical sense line to be electrically decoupled from the respective horizontal sense line.
11 more elements
A memory device, comprising:
- an array memory cells comprising a plurality of vertically stacked tiers of memory cells coupled to a plurality of horizontal access lines and to a plurality of vertical sense lines;
- semiconductor circuitry formed under the array comprising:
- a plurality of multiplexors formed under the plurality of vertically stacked tiers of memory cells, each one of the plurality of multiplexors coupled to a respective one of the plurality of vertical sense lines;
- and
- a plurality of pairs of horizontal sense lines coupled to the plurality of multiplexors;
- semiconductor circuitry formed outside of the array comprising a plurality of sense amplifiers each coupled to a respective one of the plurality of pairs of horizontal sense lines;
- and
- control circuitry configured to cause, to sense memory cells coupled to a first horizontal access line of the plurality of horizontal access lines, a first portion of the plurality of multiplexors to electrically couple a first portion of the plurality of vertical sense lines to a first one of each pair of the plurality of pairs of horizontal sense lines, wherein the first portion of the plurality of vertical sense lines is coupled to the first horizontal access line of the plurality of horizontal access line;
- wherein each of the plurality of multiplexors comprises a respective pair of transistors;
- and
- wherein the respective pair of transistors is configured such that:
- activation of a first of the respective pair of transistors causes the respective vertical sense line to be electrically coupled to the respective horizontal sense line;
- and
- activation of a second of the respective pair of transistors causes the respective vertical sense line to be electrically decoupled from the respective horizontal sense line.
11 more elements
A method of sensing a memory cell in an array, comprising:
- among a respective plurality of horizontal access lines coupled to each of a plurality of vertically stacked tiers of memory cells, activating a particular horizontal access line coupled to the memory cell;
- electrically coupling a first vertical sense line to a first horizontal sense line via a first multiplexor in semiconductor under the array circuitry, wherein the first vertical sense line is coupled to the memory cell;
- electrically coupling a second vertical sense line to a second horizontal sense line via a second multiplexor in the circuitry, wherein the second vertical sense line is not coupled to the memory cell;
- and
- sensing the memory cell with a differential sense amplifier coupled to the first horizontal sense line and the second horizontal sense line, wherein the differential sense amplifier is horizontally adjacent to the plurality of vertically stacked tiers of memory cells;
- wherein each of the first and second multiplexors comprises a respective pair of transistors;
- and
- wherein the respective pair of transistors is configured such that:
- activation of a first of the respective pair of transistors causes the respective vertical sense line to be electrically coupled to the respective horizontal sense line;
- and
- activation of a second of the respective pair of transistors causes the respective vertical sense line to be electrically decoupled from the respective horizontal sense line.
8 more elements
Dependencies are inferred from the claim text.