Apparatuses and methods for tracking row accesses

An apparatus comprising:

• a dynamic random access memory array comprising a plurality of memory banks, individual ones of the memory banks comprising a plurality of word lines;
• and
• a refresh control circuit associated with one of the plurality of memory banks configured to identify an aggressor row, the refresh control circuit comprising:
• a first register stack configured to store a first plurality of count values, wherein each of the first plurality of count values is associated with a portion of the plurality of word lines;
• a first counter circuit configured to update a. first count value of the first plurality of count values responsive to receiving at the refresh control circuit a row address associated with the portion of the plurality of word lines associated with the first count value and configured to compare the updated first count value to a first threshold and to update a second count value of the first plurality of count values responsive to receiving at the refresh control circuit a row address associated with the portion of the plurality of word lines associated with the second count value and configured to compare the updated second count value to the first threshold;
• a second register stack configured to store a second plurality of count values, wherein each of the second plurality of count values is associated with a sub-portion of the portion of the plurality of word lines associated with the first count value of the first plurality of count values;
• a second counter circuit configured to update a third count value of the second plurality of count values responsive to receiving at the refresh control circuit a row address associated with the sub-portion associated with the third count value when the first count value meets or exceeds the first threshold and configured to compare the updated third count value to a second threshold, wherein a word line associated with the row address is identified as the aggressor row when the updated third count value meets or exceeds the second threshold;
• a third register stack configured to store a third plurality of count values, wherein each of the third plurality of count values is associated with a sub-portion of the portion of the plurality of word lines associated with the second count value of the first plurality of count values;
• a third counter circuit configured to update a fourth count value of the third plurality of count values responsive to receiving at the refresh control circuit a row address associated with the sub-portion associated with the fourth count value when the second count value meets or exceeds the first threshold and configured to compare the updated fourth count value to a third threshold, wherein a word line associated with the row address is identified as the aggressor row when the updated fourth count value meets or exceeds the third threshold;
• and
• a refresh address queue configured to store a plurality of victim addresses associated with the aggressor row, wherein the refresh control circuit is configured to provide at least one of the plurality of victim of addresses for a refresh operation of a victim row associated with the at least one of the plurality of victim addresses.

An apparatus comprising:

• a dynamic random access memory array comprising a plurality of memory banks, individual ones of the memory banks comprising a plurality of word lines;
• a refresh control circuit associated with one of the plurality of memory banks configured to identify an aggressor row, the refresh control circuit comprising:
• a first register stack configured to store a first plurality of count values, wherein each of the first plurality of count values is associated with a first number of the plurality of word lines;
• a second register stack configured to store a second plurality of count values, wherein each of the second plurality of count values is associated with a second number of the plurality of word lines, wherein the second number is less than the first number;
• a third register stack configured to store a third plurality of count values, wherein each of the third plurality of count values is associated with a third number of the plurality of word lines, wherein the third number is less than the second number;
• a first counter circuit configured to update a first count value of the first plurality of count values responsive to receipt of a row address associated with the first number of the plurality of word lines associated with the first count value and configured to compare the updated first count value to a first threshold;
• a second counter circuit configured to update a second count value of the second plurality of count values responsive to receipt of a row address associated with the second number of the plurality of word lines associated with the second count value when the updated first count value meets or exceeds the first threshold and configured to compare the updated second count value to a second threshold;
• a third counter circuit configured to update a third count value of the third plurality of count values responsive to receipt of a row address associated with the third number of the plurality of word lines associated with the third count value when the updated second count value meets or exceeds the second threshold and configured to compare the updated third count value to a third threshold, wherein a word line associated with the row address is identified as the aggressor row when the updated third count value meets or exceeds the third threshold;
• and
• a refresh address queue configured to store a plurality of victim addresses associated with the aggressor row, wherein the refresh control circuit is configured to provide at least one of the plurality of victim of addresses for a refresh operation of a victim row associated with the at least one of the plurality of victim addresses.