Signal amplification in MRAM during reading, including a pair of complementary transistors connected to an array line

An apparatus, comprising:

• a cross-point memory array, the cross-point memory array comprising a memory cell, the memory cell comprising an MRAM in series with a threshold switching selector;
• a first conductive line connected to a first end of the memory cell;
• a second conductive line connected to a second end of the memory cell;
• a first transistor pair comprising a pMOSFET in parallel with an nMOSFET and connected to the first conductive line;
• a second transistor pair comprising a pMOSFET in parallel with an nMOSFET and connected to the second conductive line;
• and
• a control circuit, wherein to select the memory cell, the control circuit is configured to pull up a voltage of the first conductive line via the pMOSFET but not the nMOSFET of the first transistor pair, and to pull down a voltage of the second conductive line via the nMOSFET but not the pMOSFET of the second transistor pair, and to read the memory cell, the control circuit is configured to sense a voltage of the first conductive line a first time via the nMOSFET but not the pMOSFET of the first transistor pair.