Write protection circuit for memory and display apparatus

A write protection circuit for memory, comprising:

• a first resistor connected with a write protection pin of a memory and configured to input a low-level write control signal to the write protection pin of the memory when the memory functions normally;
• a data writing triggering terminal connected with the write protection pin of the memory and configured to output a received high-level write protection triggering signal to the write protection pin of the memory when the memory is updated in data;
• and
• an interference signal absorbing circuit connected with the data writing triggering terminal, and configured to detect a level signal received by the data writing triggering terminal when the memory functions normally and absorb the received high-level write protection triggering signal when the receiving of the high-level write protection triggering signal by the data writing triggering terminal is detected.

A display apparatus comprising a write protection circuit for memory, wherein, the write protection circuit for memory comprises:

• a data writing triggering terminal connected with a write protection pin of a memory and configured to receive a first level signal for controlling the memory to enter into a write state;
• a write protection controlling circuit connected with the write protection pin of the memory and configured to provide the write protection pin of the memory with a second level signal for restricting the memory from being written with data, wherein the second level signal is opposite in polarity to the first level signal;
• and
• an interference signal absorbing circuit connected with the data writing triggering terminal and configured to detect a level signal received by the data writing triggering terminal when the memory functions normally and absorb the first level signal when the receiving of the first level signal by the data writing triggering terminal is detected.