Systems and methods for controlling power assertion in a memory device

A method for controlling a sleep operation for a memory array that includes a memory cell and a word line driver, comprising:

• generating a word line clock signal and a delayed clock signal as a function of a memory clock signal;
• receiving the word line clock signal at the memory array, wherein the word line clock signal enables and disables memory read and write operations of the memory cell;
• generating, at a latch circuit, a local word line sleep signal in response to the delayed clock signal and one or more power management control signals;
• controlling power to the word line driver using the local word line sleep signal;
• and
• synchronizing the local word line sleep signal with the delayed clock signal such that the local word line sleep signal is prevented from turning off power to the word line driver until memory read and write operations of the memory cell are disabled by the word line clock signal.

A memory system, comprising:

• a memory array that includes a first memory cell having a first pair of word line drivers and a second memory cell having a second pair of word line drivers, the memory array receiving a word line clock signal that enables and disables memory read and write operations of the first and second memory cells;
• the memory array further including,
• a first switching circuit coupled between the first pair of word line drivers and a power source, the first switching circuit being controlled by a first local word line sleep signal to turn power to the first pair of word line drivers on and off, and
• a second switching circuit coupled between the second pair of word line drivers and the power source, the second switching circuit being controlled by a second local word line sleep signal to turn power to the second pair of word line drivers on and off;
• a latch circuit that generates the first and second local word line sleep signals in response to a delayed clock signal and one or more power management control signals,
• the word line clock signal and the delayed clock signal both being generated as a function of a memory clock signal,
• wherein the latch circuit synchronizes the first and second local word line sleep signals with the delayed clock signal such that the first and second local word line sleep signals are prevented from turning off power to the first and second pairs of word line drivers until memory read and write operations of the first and second memory cells are disabled by the word line clock signal.