Read data FIFO control circuit
AssigneeMicron Technology, Inc.
InventorRyoki Karashima
Life of this patent
Estimating the term…
Abstract
Disclosed herein is an apparatus that includes a memory cell array configured to output a read data and a timing signal in response to a read command signal, an input counter configured to update an input count value in response to the timing signal, an output counter configured to update an output count value in response to the read command signal, and a data FIFO circuit having a plurality of data registers, the data FIFO circuit being configured to store the read data into one of the data registers indicated by the input count value and configured to output the read data stored in one of the data registers indicated by the output count value. The output counter is configured to maintain the output count value without updating in response to the read command signal when an active judge signal is in an inactive state.
Claims21
An apparatus comprising:
- a memory cell array configured to receive a read command signal and output a read data. and a timing signal in response to the read command signal, wherein the read data and the timing signal are different;
- an input counter configured to receive the timing signal and update an input count value in response to the timing signal;
- an output counter configured to receive a count signal and a judge signal and update an output count value in response to the count signal and the judge signal when the judge signal is in an active state, wherein the count signal is generated based on the read command signal, and wherein the output counter is configured to maintain the output count value when the judge signal is in an inactive state;
- and
- a data FIFO circuit having a plurality of data registers, the data FIFO circuit being configured to store the read data into one of the data registers indicated by an input point value and configured to output the read data stored in one of the data registers indicated by an output point value.
An apparatus comprising:
- a memory bank configured to output a read data and a timing signal in response to a first read command signal when the memory bank is in a first state, wherein the read data and the timing signal are different;
- a latency control circuit configured to generate a second read command signal by delaying the first read command signal:
- an input counter coupled to the memory bank, wherein the input counter is configured to receive the timing signal and update an input count value in response to the timing signal;
- an output counter coupled to the latency control circuit, wherein the output counter is configured to receive the second read command signal and update an output count value in response to the second read command signal;
- a data FIFO circuit having a plurality of data registers, the data FIFO circuit being configured to store the read data into one of the data registers indicated by an input point value and configured to output the read data stored in one of the data registers indicated by an output point value;
- and
- a judge circuit coupled to the output counter, wherein the judge circuit is configured to control the output counter such that the output counter stops updating the output count value in response to the second read command signal when the first read command signal is supplied to the memory bank in a second state different from the first state.
An apparatus comprising:
- a first circuit configured to output second and third signals when a first period is elapsed after a first signal is received, wherein the second and third signals are different;
- a second circuit configured to output fourth signal when a second period greater than the first period is elapsed after the first signal is received;
- an input counter coupled to the first circuit and configured to receive the third signal and update an input count value in response to the third signal;
- an output counter coupled to the second circuit and configured to receive the fourth signal and update an output count value in response to the fourth signal;
- a FIFO circuit having a plurality of registers, the FIFO circuit being configured to store the second signal into one of the registers indicated by an input point value and configured to output the second signal stored in one of the registers indicated by an output point value, and
- a third circuit coupled to the output counter and configured to control the output counter such that the output counter stops updating the output count value in response to the fourth signal when the first signal is supplied to the first circuit in an inactive state.
Dependencies are inferred from the claim text.