System device and method for providing single port memory access in bitcell array by tracking dummy wordline

A device, comprising:

• single port memory architecture having a bitcell array;
• multiple wordlines coupled to multiple columns of the bitcell array;
• and
• logic circuitry that performs multiple memory access operations concurrently in the single port memory architecture including performing a read operation in one column of the bitcell array using one wordline of the multiple wordlines while performing a write operation at the same time in another column of the bitcell array using another wordline of the multiple wordlines, or performing a write operation in one column of the bitcell array using one wordline of the multiple wordlines while performing a read operation at the same time in another column of the bitcell array using another wordline of the multiple wordlines;
• wherein the logic circuitry tracks a dummy wordline having fixed delays coupled along a self-timed path of the dummy wordline.

A system, comprising:

• a processor;
• and
• memory having stored thereon instructions that, when executed by the processor, cause the processor to:
• access single port memory having a bitcell array;
• access dual wordlines of the single port memory including accessing columns of the bitcell array with the dual wordlines;
• perform multiple memory access operations concurrently in the single port memory including performing a read operation in one column of the bitcell array using a first wordline of the dual wordlines while performing a write operation in another column of the bitcell array using a second wordline of the dual wordlines, or performing a write operation in one column of the bitcell array using the first wordline of the dual wordlines while performing a read operation in another column of the bitcell array using the second wordline of the dual wordlines;
• and
• track a dummy wordline having fixed delays coupled along a self-timed path of the dummy wordline.