Computational architecture for active noise reduction device

A personal active noise reduction (ANR) device, comprising:

• a communication interface configured to receive a source audio stream and control signals;
• a driver;
• a microphone system;
• and
• an ANR computational architecture, comprising:
• a first DSP processor configured to:
• receive the source audio stream and signals from the microphone system, perform ANR on the source audio stream according to a core algorithm that utilizes a set of operational parameters stored in the first DSP processor, and output a processed audio stream to the driver;
• a second DSP processor configured to:
• generate state data in response to an analysis of at least one of the source audio stream, signals from the microphone system, and the processed audio stream;
• and communicate signals to the first DSP processor over a common bus to alter the set of operational parameters stored in the first DSP processor;
• and
• a general purpose processor operationally coupled to the first DSP processor and the second DSP processor and configured to:
• communicate control signals with the communication interface, process state data from the second DSP processor, and alter the set of operational parameters stored in the first DSP processor;
• wherein the first DSP processor and the second DSP processor share signals over the common bus that is also accessible by the general purpose processor, and wherein the first DSP processor and second DSP processor operate at different speeds in which the first DSP processor functions with a lower latency relative to the second DSP processor.