Drive method, display panel and driving circuit

A display panel, comprising:

• a plurality of data lines;
• a plurality of gate lines intersected with the data lines;
• and
• a plurality of pixels respectively driven by corresponding data lines and gate lines, each of the plurality of pixels comprising a corresponding pixel electrode, a same gate line is connected to two adjacent pixels to form a pixel group, and the pixel group comprises a first pixel and a second pixel connected to different data lines;
• wherein a pixel electrode of the first pixel of the pixel group overlaps with a previous gate line to form a first overlap region, and a pixel electrode of the second pixel of the pixel group overlaps with a next gate line to form a second overlap region;
• wherein the display panel further comprises a driving circuit for driving the display panel, wherein the driving circuit is configured to output a gate driving signal to a corresponding gate line of the display panel;
• wherein a signal period of the gate driving signal comprises a hold time, an open time, and a first pull-down time adjacent to the open time, the gate driving signal is in a first low level within the hold time, the gate driving signal is in a high level at the open time, the gate driving signal is in a second low level within the first pull-down time, and a voltage value of the second low level is lower than a voltage value of the first low level;
• wherein the first pull-down time is before the open time the signal period of the gate driving signal further comprises a second pull-down time after the open time, the gate driving signal is in a third low level within the second pull-down time, and a voltage value of the third low level is lower than the voltage value of the first low level;
• wherein the first pull-down time and the open time are equal in duration;
• wherein a gate driving signal of a current gate line corresponds to the first pull-down time when a gate driving signal of a previous gate line corresponds to the open time;
• wherein the open time and the second pull-down time are equal in duration;
• wherein the area of the first overlap region is S1, a storage capacitance formed by overlapping the first overlap region of the first pixel with the previous gate line is Cst1, a pixel capacitance of the first pixel is Clc1, and a parasitic capacitance formed by the pixel electrode of the first pixel and the current gate line is Cgs1;
• wherein the voltage values of the first low level and the third low level are V′GL, the voltage value of the high level is VGH, and the voltage value of the second low level is VGL;
• Cst1=(VGH−VGL)*Cgs1/(VGL−V′GL).

A driving circuit for driving a display panel, the display panel comprising:

• a plurality of pixels formed by a plurality of data lines intersecting a plurality of gate lines;
• each of the plurality of pixels comprises a pixel electrode;
• a same gate line is connected to two adjacent pixels to form a pixel group, and the pixel group comprises a first pixel and a second pixel connected to different data lines;
• wherein a pixel electrode of the first pixel of the pixel group overlaps with a previous gate line to form a first overlap region, and a pixel electrode of the second pixel of the pixel group overlaps with a next gate line to form a second overlap region;
• the driving circuit comprises:
• a gate driving circuit configured to output a gate driving signal to a corresponding gate line of the display panel;
• wherein a signal period of the gate driving signal output by the gate driving circuit comprises a hold time, an open time, and a first pull-down time adjacent to the open time, the gate driving signal is in a first low level within the hold time, the gate driving signal is in a high level at the open time, the gate driving signal is in a second low level within the first pull-down time, and a voltage value of the second low level is lower than a voltage value of the first low level;
• wherein the first pull-down time is before the open time, the signal period of the gate driving signal further comprises a second pull-down time after the open time, the gate driving signal is in a third low level within the second pull-down time, and a voltage value of the third low level is lower than the voltage value of the first low level;
• wherein the first pull-down time and the open time are equal in duration;
• wherein a gate driving signal of a current gate line corresponds to the first pull-down time when a gate driving signal of a previous gate line corresponds to the open time;
• wherein the open time and the second pull-down time are equal in duration;
• wherein the area of the first overlap region is S1, a storage capacitance formed by overlapping the first overlap region of the first pixel with the previous gate line is Cst1, a pixel capacitance of the first pixel is Clc1, and a parasitic capacitance formed by the pixel electrode of the first pixel and the current gate line is Cgs1;
• the voltage values of the first low level and the third low level are V′GL, the voltage value of the high level is VGH, and the voltage value of the second low level is VGL:
• Cst1=(VGH−VGL)*Cgs1/(VGL−V′GL).