Display apparatus

A display apparatus comprising:

• a plurality of pixels configured to display an image,
• wherein each of at least one of the plurality of pixels includes a pixel circuit and a light emitting device connected to the pixel circuit,
• wherein a plurality of signals are configured to drive the plurality of pixels according to an initialization period, a programming period, a sampling period, and an emission period,
• wherein the plurality of signals includes:
• a first scan signal having a high level in the initialization period and the sampling period, and having a low level in the programming period and the emission period;
• and
• a second scan signal having a high level in the programming period and the sampling period, and having a low level in the initialization period and the emission period,
• wherein the pixel circuit includes:
• a driving transistor turned on based on a voltage of a fourth node which is a gate electrode of the driving transistor and selectively connecting a first node which is at a source electrode of the driving transistor to a third node which is a drain electrode of the driving transistor;
• a data supply transistor selectively providing a data voltage to the first node which is at the source electrode of the driving transistor;
• a first light emitting control transistor configured to selectively connect the first node to a second node which is an anode electrode of the light emitting device;
• a first scan line connected to a gate electrode of a first initialization transistor and a gate electrode of a second initialization transistor which is configured to selectively connect the third node to the fourth node;
• and
• a second scan line connected to a gate electrode of the data supply transistor,
• a voltage of the second node being dropped in synchronization with a falling time of the first scan signal of the sampling period, and
• wherein the first scan line supplies the first scan signal and the second scan line supplies the second scan signal.

A display apparatus comprising:

• a plurality of pixels configured to display an image,
• wherein each of at least one of the plurality of pixels includes a pixel circuit and a light emitting device connected to the pixel circuit,
• wherein a plurality of signals are configured to drive the plurality of pixels according to an initialization period, a programming period, a sampling period, and an emission period,
• wherein the plurality of signals includes:
• a first scan signal having a high level in the initialization period and the sampling period, and having a low level in the programming period and the emission period;
• and
• a second scan signal having a high level in the programming period and the sampling period, and having a low level in the initialization period and the emission period,
• wherein the pixel circuit includes:
• a driving transistor turned on based on a voltage of a fourth node which is a gate electrode of the driving transistor and selectively connecting a first node which is at a source electrode of the driving transistor to a third node which is a drain electrode of the driving transistor;
• a data supply transistor selectively providing a data voltage to the first node which is at the source electrode of the driving transistor;
• a first light emitting control transistor configured to selectively connect the first node to a second node which is an anode electrode of the light emitting device;
• a first scan line connected to a gate electrode of a first initialization transistor and a gate electrode of a second initialization transistor which is configured to selectively connect the third node to the fourth node;
• and
• a second scan line connected to a gate electrode of the data supply transistor,
• a voltage of the second node being dropped in synchronization with a falling time of the second scan signal after the sampling period, and
• wherein the first scan line supplies the first scan signal and the second scan line supplies the second scan signal.