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US 11,386,827 B1Granted
Level shifter and display device
AssigneeLG Display Co., Ltd.
InventorsHoon Jang, Soondong Cho
Life of this patent
Estimating the term…
Abstract
Embodiments of the present disclosure relate to a level shifter and a display device capable of differently controlling a signal waveform between a first clock signal and a second clock signal used to output a first gate signal and a second gate signal. Accordingly, it is possible to reduce the variation in output characteristics between the first gate signal and the second gate signal, thereby improving image quality.
Claims20
A level shifter comprising:
- a first output terminal outputting a first clock signal;
- a second output terminal outputting a second clock signal having a different rising length or a different falling length than a rising length or a falling length of the first clock signal, respectively;
- a high input terminal to which a high level voltage is input;
- a low input terminal to which a low level voltage is input, the low level voltage less than the high level voltage;
- an intermediate input terminal to which an intermediate level voltage is input, the intermediate level voltage less than the high level voltage and greater than the low level voltage;
- a first clock output circuit including a first rising switch configured to control an electrical connection between the high input terminal and the first output terminal, a first falling switch configured to control an electrical connection between the low input terminal and the first output terminal, and a first gate pulse modulation switch configured to control an electrical connection between the intermediate input terminal and the first output terminal;
- and
- a second clock output circuit including a second rising switch configured to control an electrical connection between the high input terminal and the second output terminal, a second falling switch configured to control an electrical connection between the low input terminal and the second output terminal, and a second gate pulse modulation switch configured to control an electrical connection between the intermediate input terminal and the second output terminal.
5 more elements
A display device comprising:
- a substrate;
- a plurality of gate lines disposed on the substrate;
- and
- a gate driving circuit disposed on or connected to the substrate and configured to output a first gate signal and a second gate signal to a first gate line and a second gate line among the plurality of gate lines based on a first clock signal and a second clock signal,
- wherein the gate driving circuit comprises:
- a first gate output buffer circuit configured to output the first gate signal based on the first clock signal;
- a second gate output buffer circuit configured to output the second gate signal based on the second clock signal;
- and
- a gate output control circuit configured to control the first gate output buffer circuit and the second gate output buffer circuit,
- wherein the first gate output buffer circuit comprises:
- a first pull-up transistor connected between a first clock input terminal to which the first clock signal is input and a first gate output terminal to which the first gate signal is output;
- and
- a first pull-down transistor connected between the first gate output terminal and a base input terminal to which a base voltage is input,
- wherein the second gate output buffer circuit comprises:
- a second pull-up transistor connected between a second clock input terminal to which the second clock signal is input and a second gate output terminal to which the second gate signal is output;
- and
- a second pull-down transistor connected between the second gate output terminal and a base input terminal to which a base voltage is input,
- wherein a gate node of the first pull-up transistor and a gate node of the second pull-up transistor are electrically connected,
- wherein a gate node of the first pull-down transistor and a gate node of the second pull-down transistor are electrically connected, and
- wherein a falling length of the first clock signal is different from a falling length of the second clock signal, or a rising length of the second clock signal is different from a rising length of the first clock signal.
17 more elements
Dependencies are inferred from the claim text.