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US 11,386,321 B2Granted
Neural network circuit
AssigneeHitachi, Ltd.
InventorsTakashi Oshima, Atsutake Kosuge, Taizo Yamawaki
Life of this patent
Estimating the term…
Abstract
A neural network circuit having a plurality of analog-to-digital multipliers generates an analog product-sum voltage corresponding to the sum of charge signals of each of the analog-to-digital multipliers.
Claims13
A neural network circuit, comprising:
- a plurality of D/A converters configured to convert a digital input signal into an analog input voltage;
- a plurality of analog-to-digital multipliers each connected to the D/A converters and configured to output a predetermined multiplication result obtained by multiplying the analog input voltage by a weighting factor which is a digital signal;
- a capacitance configured to hold an addition result obtained by adding a plurality of the multiplication results;
- an analog activation function circuit configured to perform analog processing corresponding to an activation function on the addition result;
- and
- a switch configured to discharge an alternating current component of a charge on the capacitor,
- wherein each of the analog-to-digital multipliers includes an output node to which the analog-to-digital input voltage is connected, and a MOS transistor provided corresponding to at least one bit signal corresponding to the digital signal,
- the MOS transistor has a source terminal, a drain terminal, and a gate terminal,
- the source terminal and the drain terminal are connected to the output node,
- a voltage based on the bit signal is applied to the gate terminal,
- a charge signal corresponding to the product of the analog input voltage and the bit signal is output as the multiplication result, and
- a plurality of the analog-to-digital multipliers generates an analog product-sum voltage corresponding to the sum of the charge signals of each of the analog-to-digital multipliers on the capacitance by connecting the output nodes.
9 more elements
A neural network circuit, comprising:
- a plurality of D/A converters configured to convert a digital input signal into an analog input voltage;
- a plurality of analog-to-digital multipliers each connected to the D/A converters and configured to output a predetermined multiplication result obtained by multiplying the analog input voltage by a weighting factor which is a digital signal;
- a capacitance configured to hold an addition result obtained by adding a plurality of the multiplication results;
- an analog activation function circuit configured to perform analog processing corresponding to an activation function on the addition result;
- and
- a switch configured to discharge an alternating current component of a charge on the capacitor,
- wherein each of the analog-to-digital multipliers includes an output node to which the analog-to-digital input voltage is connected, and a MOS transistor provided corresponding to at least one bit signal corresponding to the digital signal,
- the MOS transistor has a source terminal, a drain terminal, and a gate terminal,
- the gate terminal and the drain terminal are connected to the output node,
- a voltage based on the bit signal is applied to the source terminal and the drain terminal,
- a charge signal corresponding to the product of the analog input voltage and the bit signal is output as the multiplication result, and
- a plurality of the analog-to-digital multipliers generates an analog product-sum voltage corresponding to the sum of the charge signals of each of the analog-to-digital multipliers on the capacitance by connecting the output nodes.
9 more elements
A neural network circuit, comprising:
- a plurality of first D/A converters configured to convert a digital input signal into an analog input voltage;
- a plurality of analog-to-digital multipliers each connected to the first D/A converters and configured to output a predetermined multiplication result, as an analog signal, obtained by multiplying the analog input voltage by a weighting factor which is a digital signal;
- a capacitance configured to hold an addition result obtained by adding a plurality of the multiplication results;
- an A/D converter configured to convert the addition result that is an analog voltage into a digital signal;
- a digital activation function circuit configured to perform digital processing corresponding to an activation function on the addition result as the digital signal output from the A/D converter;
- a second D/A converter configured to convert a digital output signal of the digital activation function circuit into an analog voltage;
- and
- a switch configured to discharge an alternating current component of a charge on the capacitor,
- wherein each of the analog-to-digital multipliers includes an output node to which the analog-to-digital input voltage is connected, and a MOS transistor provided corresponding to at least one bit signal corresponding to the digital signal,
- the MOS transistor has a source terminal, a drain terminal, and a gate terminal,
- the source terminal and the drain terminal are connected to the output node,
- a voltage based on the bit signal is applied to the gate terminal,
- a charge signal corresponding to the product of the analog input voltage and the bit signal is output as the multiplication result, and
- a plurality of the analog-to-digital multipliers generates an analog product-sum voltage corresponding to the sum of the charge signals of each of the analog-to-digital multipliers on the capacitance by connecting the output nodes.
11 more elements
Dependencies are inferred from the claim text.