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US 11,386,254 B2Granted
Semiconductor circuit and semiconductor circuit layout system
AssigneeSamsung Electronics Co., Ltd.
InventorsAh Reum Kim, Min Su Kim, Young O Lee
Life of this patent
Estimating the term…
Abstract
A semiconductor circuit and a layout system of the semiconductor circuit, the semiconductor circuit including a latch; a feedback inverter that receives an output signal of the latch via a first node and provides a feedback signal to the latch responsive to the output signal of the latch; and an output driver which receives the output signal of the latch via the first node and provides an output signal externally of the semiconductor circuit. The output driver includes an even number of inverters, and the latch, the feedback inverter, and the output driver share a single active region formed without isolation.
Claims20
A semiconductor circuit comprising:
- a latch;
- a feedback inverter configured to receive an output signal of the latch via a first node and to provide a feedback signal to the latch responsive to the output signal of the latch;
- and
- an output driver configured to receive the output signal of the latch via the first node and to provide an output signal externally of the semiconductor circuit,
- wherein the output driver includes an even number of inverters, and
- the latch, the feedback inverter, and the output driver share a single active region formed without isolation.
3 more elements
A semiconductor circuit comprising:
- a first PMOS transistor disposed on a first gate line to which a signal of a first node is applied and that provides a power supply voltage to a second node responsive to the signal at the first node;
- a first NMOS transistor disposed on the first gate line and that provides a ground voltage to the second node responsive to the signal at the first node,
- the first PMOS transistor and the first NMOS transistor configured as a feedback inverter;
- a second PMOS transistor disposed on a second gate line to which the signal of the first node is applied and that is disposed adjacent to the first gate line, and that provides the power supply voltage to a third node responsive to the signal at the first node;
- a second NMOS transistor disposed on the second gate line and that provides the ground voltage to the third node responsive to the signal at the first node;
- a third PMOS transistor disposed on a third gate line to which the signal of the first node is applied and that is disposed adjacent to the second gate line, and that provides the power supply voltage to the third node responsive to the signal at the first node;
- and
- a third NMOS transistor disposed on the third gate line and that provides the ground voltage to the third node responsive to the signal at the first node,
- the second PMOS transistor, the second NMOS transistor, the third PMOS transistor and the third NMOS transistor configured as an output driver,
- wherein the output driver shares the power supply voltage and the ground voltage with a latch, the power supply voltage and the ground voltage are respectively applied through a first VDD power contact and a first VSS power contact disposed between the output driver and the latch that receives a signal at the second node as a feedback input, and
- the output driver shares the power supply voltage and the ground voltage with the feedback inverter, the power supply voltage and the ground voltage are respectively applied through a second VDD power contact and a second VSS power contact disposed between the feedback inverter and the output driver.
8 more elements
A semiconductor circuit comprising:
- a latch which receives a signal of a first node as a feedback signal via a second node;
- a first PMOS transistor disposed on a first gate line to which the signal of the first node is applied and which is disposed adjacent to one side of the latch, and that provides a power supply voltage to the second node responsive to the signal of the first node;
- a first NMOS transistor disposed on the first gate line and that provides a ground voltage to the second node responsive to the signal of the first node,
- the first PMOS transistor and the first NMOS transistor configured as a feedback inverter;
- a second PMOS transistor disposed on a second gate line to which the signal of the first node is applied and which is disposed adjacent to another side of the latch, and that provides the power supply voltage to a third node responsive to the signal of the first node;
- a second NMOS transistor disposed on the second gate line and that provides the ground voltage to the third node responsive to the signal of the first node;
- a third PMOS transistor disposed on a third gate line to which the signal of the first node is applied and which is disposed adjacent to the second gate line, and that provides the power supply voltage to the third node responsive to the signal of the first node;
- and
- a third NMOS transistor disposed on the third gate line and that provides the ground voltage to the third node responsive to the signal of the first node,
- the second PMOS transistor, the second NMOS transistor, the third PMOS transistor and the third NMOS transistor configured as an output driver,
- wherein the feedback inverter shares the power supply voltage and the ground voltage with the latch, the power supply voltage and the ground voltage are respectively applied through a first VDD power contact and a first VSS power contact disposed between the latch and the feedback inverter, and
- the output driver shares the power supply voltage and the ground voltage with the latch, the power supply voltage and the ground voltage are respectively applied through a second VDD power contact and a second VSS power contact disposed between the latch and the output driver.
9 more elements
Dependencies are inferred from the claim text.