Power-aware scan partitioning

A method for partitioning circuit cells of a circuit design into scan groups useable to form scan chains in the circuit design, the method comprising:

• calculating a power score for each of a plurality of circuit cells within a circuit design based on one or more physical cell parameters of the plurality of circuit cells used in the circuit design;
• sorting the plurality of circuit cells according to the power score;
• defining a plurality of scan groups;
• selecting a highest unassigned circuit cell of the plurality of circuit cells;
• assigning the highest unassigned circuit cell to a scan group of the plurality of scan groups having a lowest aggregate power score.

A system for partitioning circuit cells of a circuit design into scan groups useable to form scan chains in the circuit design, the system comprising:

• a programmable circuit;
• a memory operatively connected to the programmable circuit, the memory storing instructions which, when executed by the programmable circuit, cause the system to perform:
• calculating a power score for each of a plurality of circuit cells within a circuit design based on one or more physical cell parameters of the plurality of circuit cells used in the circuit design;
• sorting the plurality of circuit cells according to the power score;
• defining a plurality of scan groups;
• selecting a highest unassigned circuit cell of the plurality of circuit cells;
• assigning the highest unassigned circuit cell to a scan group of the plurality of scan groups having a lowest aggregate power score;
• determine whether a power score for the circuit design including the plurality of scan groups is above a threshold;
• and,
• based on a determination that the power score is above a threshold, ordering a plurality of circuit blocks included in a scan group into a scan chain based at least in part on minimization of an interconnect power score defined by power consumption of interconnects between consecutive flops in the scan chain.