US 11,386,252 B1 · Techniques for simulation-based timing path labeling for multi-operating condition frequency prediction

Abstract

Techniques improve integrated circuit design by employing multi-operating condition frequency prediction for statically timed designs through spice-based timing path labeling and statistical analysis. Design management component (DMC) can randomly determine and generate sample timing paths based on parameters of characteristics associated with the sample timing paths, the parameters determined based on random seed values; simulate responses of the sample timing paths; and generate vectorized data based on the simulated responses. DMC determines a trained model representing timing path properties and operating conditions of sample timing paths based on statistical analysis of vectorized data. Static timing analysis (STA) component can perform STA on design information of integrated circuitry design and determine an operating condition of a timing path of the design based on the STA. DMC can determine or predict another operating condition(s) associated with the design based on the operating condition and the trained model.

Claims20

Dependent claims

A method for determining timing path frequency associated with an integrated circuitry design, comprising:

determining, by a system comprising a processor, respective agnostic timing paths of a set of agnostic timing paths based at least in part on respective characteristics associated with the respective agnostic timing paths, wherein the respective characteristics are determined based at least in part on respective random seed values;
determining, by the system, a trained model that represents timing path properties and operating conditions of the set of agnostic timing paths based at least in part on an analysis of vectorized information determined from timing path information relating to the respective characteristics associated with the respective agnostic timing paths;
determining, by the system, an operating condition of a timing path of the integrated circuitry design based at least in part on a static timing analysis performed on design data associated with the integrated circuitry design;
and
determining, by the system, at least one other operating condition associated with the integrated circuitry design based at least in part on the operating condition and the trained model that represents the timing path properties and the operating conditions of the set of agnostic timing paths.

2 more elements

A method of improving integrated circuit design by employing multi-operating condition frequency prediction for statically timed designs, comprising:

determining, by a system comprising a processor, respective agnostic timing paths of a set of agnostic timing paths based at least in part on respective characteristics associated with the respective agnostic timing paths, wherein the respective characteristics are determined based at least in part on respective random seed values;
determining, by the system, a trained model that represents timing path properties and operating conditions of the set of agnostic timing paths based at least in part on an analysis of vectorized information determined from timing path information relating to the respective characteristics associated with the respective agnostic timing paths;
determining, by the system, an operating condition of a timing path of the integrated circuitry design based at least in part on a static timing analysis performed on design data associated with the integrated circuitry design;
and
determining, by the system, at least one other operating condition associated with the integrated circuitry design based at least in part on the operating condition and the trained model that represents the timing path properties and the operating conditions of the set of agnostic timing paths.

2 more elements

Dependencies are inferred from the claim text.

Techniques for simulation-based timing path labeling for multi-operating condition frequency prediction

Life of this patent

Techniques for simulation-based timing path labeling for multi-operating condition frequency prediction

Life of this patent

Abstract

Claims20