Masked gate logic for resistance to power analysis
AssigneeCryptography Research, Inc.
InventorsAndrew John Leiserson, Mark Evan Marson, Megan Anneke Wachs
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AssigneeCryptography Research, Inc.
InventorsAndrew John Leiserson, Mark Evan Marson, Megan Anneke Wachs
Estimating the term…
A method of and system for gate-level masking of secret data during a cryptographic process is described. A mask share is determined, wherein a first portion of the mask share includes a first number of zero-values and a second number of one-values, and a second portion of the mask share includes the first number of one-values and the second number of zero-values. Masked data values and the first portion of the mask share are input into a first portion of masked gate logic, and the masked data values and the second portion of the mask share are input into a second portion of the masked gate logic. A first output from the first portion of the masked gate logic and a second output from the second portion of the masked gate logic are identified, wherein either the first output or the second output is a zero-value.
A system comprising:
A circuit comprising:
A system comprising:
Dependencies are inferred from the claim text.