High throughput circuit architecture for hardware acceleration

A method of hardware acceleration, comprising:

• receiving a plurality of descriptors and a plurality of addresses for the plurality of descriptors via a switch of a hardware acceleration device, wherein the switch is communicatively linked to a host central processing unit (CPU);
• wherein the descriptors specify operations to be performed by a compute circuit of the hardware acceleration device;
• conveying the plurality of descriptors to a random-access memory for storage therein via a data bus;
• conveying the plurality of addresses to an adapter circuit via a control bus;
• wherein the host CPU initiates register writes to write the plurality of addresses of the descriptors over the control bus to registers within the adapter circuit;
• and
• using the adapter circuit, retrieving the plurality of descriptors from the random-access memory via the data bus using the plurality of addresses received over the control bus, providing arguments from the descriptors to the compute circuit, and providing control signals to the compute circuit to initiate the operations using the arguments.