Extending multichip package link off package

An apparatus comprising:

• an integrated circuit package;
• and
• a physical layer interface to couple the integrated circuit package to an interface of another integrated circuit package over a link, wherein the physical layer interface comprises:
• a set of control conductors to support a set of control signals, wherein the set of control signals comprise control signals to cause transitions in link states according to a state machine;
• a plurality of data lanes to receive data from components of the other integrated circuit package;
• and
• a set of valid signal conductors to support receipt of a valid signal, wherein the valid signal indicates whether data received on the plurality of data lanes comprises valid data, and receipt of data on the plurality of data lanes is to be aligned with transmission of the valid signal on the valid signal channel.

A method comprising:

• identifying a clock signal for an interface, wherein the interface is to couple an integrated circuit package to another device outside the integrated circuit package over a physical link, the interface comprises a set of control channels, a valid channel, and a separate plurality of data lanes;
• sending a control signal over the link on a control channel of the interface, wherein the control signal is to cause transitions in link states according to a state machine;
• identifying particular data to be sent to the other device;
• sending a valid signal over the link on a dedicated valid channel of the interface, wherein the valid signal corresponds to the particular data;
• and
• sending the particular data over the link on the plurality of data lanes to align with the valid signal.

A system comprising:

• a computing device;
• an integrated circuit package comprising:
• computing hardware;
• and
• a physical layer interface to couple the integrated circuit package to the computing device over a physical interconnect, wherein the physical layer interface comprises:
• a clock lane to support a clock signal;
• a control interface comprising one or more control lanes to support a set of control signals, wherein the set of control signals comprise control signals to cause transitions in link states according to a state machine;
• a plurality of data lanes to transmit data;
• and
• a valid signal channel comprising one or more valid lanes to support transmission of a valid signal, wherein transmission of data on the data lanes is to be aligned with transmission of the valid signal on the valid signal channel.