Programmable device configuration memory system

A programmable device, comprising:

• a programmable fabric;
• a configuration memory for storing data to configure the programmable fabric, the configuration memory comprising a plurality of frames;
• a configuration memory read/write unit configured to receive configuration data for storage in the configuration memory;
• a plurality of configuration memory read/write controllers coupled to the configuration memory read/write unit;
• and
• a plurality of fabric sub-regions (FSRs) respectively coupled to the plurality of configuration memory read/write controllers, each FSR including a pipeline of memory cells of the configuration memory disposed between buffers and a configuration memory read/write pipeline unit coupled between the pipeline and a next one of the plurality of FSRs and to a respective one of the plurality of configuration memory read/write controllers, wherein the configuration memory read/write pipeline unit in each of the plurality of FSRs includes:
• a flip-flop having an output coupled to the respective one of the plurality of configuration memory read/write controllers;
• and
• a multiplexer having an output coupled to an input of the flip-flop, a first input coupled to the respective one of the plurality of configuration memory read/write controllers, and a second input coupled to one of the buffers in the respective FSR.

A method of configuring a programmable device, comprising:

• receiving, at configuration memory read/write unit, configuration data for storage in a configuration memory of the programmable device, the configuration memory comprising a plurality of frames;
• providing the configuration data to a plurality of configuration memory read/write controllers coupled to the configuration memory read/write unit;
• and
• providing the configuration data from the plurality of configuration memory read/write controllers to a plurality of fabric sub-regions (FSRs) respectively coupled to the plurality of configuration memory read/write controllers, each FSR including a pipeline of memory cells of the configuration memory disposed between buffers and a configuration memory read/write pipeline unit coupled between the pipeline and a next one of the plurality of FSRs and to a respective one of the plurality of configuration memory read/write controllers, wherein the configuration memory read/write pipeline unit in each of the plurality of FSRs includes:
• a flip-flop having an output coupled to the respective one of the plurality of configuration memory read/write controllers;
• and
• a multiplexer having an output coupled to an input of the flip-flop, a first input coupled to the respective one of the plurality of configuration memory read/write controllers, and a second input coupled to one of the buffers in the respective FSR.