Usage of data mask in DRAM write

A controller for a data storage device, comprising:

• an input/output (I/O) to one or more memory devices;
• and
• a processor configured to execute a method for masking errors in a dynamic random access memory (DRAM) write, wherein the method comprises:
• issuing a read command for read data, that includes read alignment data;
• issuing a write command;
• detecting an error in read data;
• masking bytes of the read data that are indicated as having an error, wherein a location of the masked bytes is tracked by a logic analyzer coupled to the controller, and wherein tracking the location increases visibility of the masked bytes;
• combining the read data and write data to form partial write data;
• and
• writing the partial write data to the one or more memory devices based on the read alignment data.

A system for storing data, comprising:

• one or more memory means;
• a logic analyzer;
• and
• a controller coupled to the one or more memory means and the logic analyzer, wherein the controller is configured to carry out a method for masking errors in a dynamic random access memory (DRAM) write, and wherein the method comprises:
• executing a partial write command, wherein executing a partial write command comprises:
• issuing a read data command;
• issuing a write command comprising write data;
• receiving read data from the one or more memory means;
• receiving byte alignment data;
• modifying the write data based on the byte alignment data;
• detecting an error in a byte of the modified write data;
• masking the byte, wherein a location of the masked byte is tracked by the logic analyzer, and wherein tracking the location increases visibility of the masked byte;
• and
• combining the read data, write data, and masked byte.