Adaptive parity techniques for a memory device
AssigneeMicron Technology, Inc.
InventorsJustin Eno, William A. Melton, Sean S. Eilert
Life of this patent
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Abstract
Methods, systems, and devices for adaptive parity techniques for a memory device are described. An apparatus, such as a memory device, may use one or more error correction code (ECC) schemes, an error cache, or both to support access operations. The memory device may receive a command from a host device to read or write data. If the error cache includes an entry for the data, the memory device may read or write the data using a first ECC scheme. If the error cache does not include an entry for the data, the memory device may read or write the data without using an ECC scheme or using a second ECC scheme different than the first ECC scheme.
Claims25
A method, comprising:
- receiving a command to read data from a memory array, the command indicating an address associated with the data;
- reading the data from the memory array in response to the command;
- determining, based at least in part on the address, whether a cache includes an indication of the address and a set of parity bits for the data;
- and
- checking the data for one or more errors using the set of parity bits based at least in part on whether the cache includes the indication of the address and the set of parity bits.
A method, comprising:
- receiving a command to write data to a memory array, the command indicating an address associated with the data;
- determining, in response to the command, whether a cache includes an indication of the address;
- generating a set of parity bits for the data based at least in part on whether the cache includes the indication of the address;
- and
- writing the data to the memory array and the set of parity bits to the cache.
An apparatus, comprising:
- a memory array,
- a cache configured to store a plurality of entries each corresponding to a respective set of memory cells within the memory array, each entry of the plurality comprising an indication of an address associated with the respective set of memory cells, parity bits for data associated with the respective set of memory cells, or a combination thereof, and
- circuitry configured to cause the apparatus to:
- receive a command to read data from the memory array, the command indicating an address associated with the data;
- read the data from the memory array in response to the command;
- determine, based at least in part on the address, whether the cache includes an entry associated with the address and a set of parity bits for the data;
- and
- check the data for one or more errors using the set of parity bits based at least in part on whether the cache includes the entry associated with the address and the set of parity bits.
Dependencies are inferred from the claim text.