Merge execution unit for microinstructions
AssigneeMarvell Asia Pte Ltd
InventorDavid A. Carlson
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Abstract
A merge unit configured to perform merge and permutation micro-operations by multiplexing data bytes of the inputs to simultaneously produce multiple data bytes of a merge and permutation result. Particularly, the merge unit includes a bank of MUXs arranged in parallel, each corresponding to one or more different data bytes in the merge result. When the merge unit is provided with a set of inputs, each MUX multiplexes the data bytes of the set of inputs (e.g., all the data bytes of the set of inputs) to selectively output a data byte to a particular location of the destination register storing the merge result. The selection by each MUX is individually controlled by a set of merge control words which identify a data byte location in an input and identify an input from the set of inputs.
Claims20
A method of executing machine instructions in a processor, said method comprising:
- fetching an instruction comprising an opcode and a set of operands;
- decoding said opcode to generate a set of merge control words;
- feeding a first set of inputs and said set of merge control words to a merge execution unit comprised in said processor, wherein said first set of inputs comprises at least a first operand of said set of operands, and wherein said set of merge control words controls said merge execution unit to select data units from said first set of inputs;
- and
- generating, by said merge execution unit, a merge result comprising a first plurality of data units comprising the selected data units, wherein said generating comprises permuting said selected data units, and wherein said permuting comprises using said set of merge control words to multiplex said selected data units.
A processor configured to execute instructions, said processor comprising:
- a fetcher configured to fetch an instruction comprising an opcode and a set of operands;
- a decoder coupled to said fetcher and configured to decode said opcode to generate a set of merge control words;
- and
- a merge execution unit coupled to said decoder and comprising a bank of multiplexers arranged in parallel and configured to:
- i) receive a first set of inputs comprising at least one operand of said set of operands, ii) select data units from said first set of inputs according to said set of merge control words, and iii) multiplex the selected data units according to said set of merge control words, to generate a merge result that comprises a plurality of data units comprising said selected data units.
A system comprising:
- a memory;
- and
- a processor coupled to said memory and comprising:
- a fetcher configured to fetch an instruction comprising an opcode and a set of operands;
- a decoder coupled to said fetcher and configured to decode said opcode to generate a set of merge control words;
- and
- a merge execution unit coupled to said decoder and comprising a bank of multiplexers arranged in parallel, and configured to:
- i) receive a first set of inputs comprising at least one operand of said set of operands, ii) select data units from said first set of inputs according to said set of merge control words, and iii) multiplex the selected data units according to said set of merge control words, to generate a merge result that comprises a plurality of data units comprising said selected data units.
Dependencies are inferred from the claim text.