US 11,385,894 B2 · Processor circuit and data processing method

Abstract

A processor circuit is provided. The processor circuit includes an instruction decode unit, an instruction detector, an address generator and a data buffer. The instruction decode unit is configured to decode a load instruction to generate a decoding result. The instruction detector, coupled to the instruction decode unit, is configured to detect if the load instruction is in a load-use scenario. The address generator, coupled to the instruction decode unit, is configured to generate a first address requested by the load instruction according to the decoding result. The data buffer is coupled to the instruction detector and the address generator. When the instruction detector detects that the load instruction is in the load-use scenario, the data buffer is configured to store the first address generated from the address generator, and store data requested by the load instruction according to the first address.

Claims20

Dependent claims

A processor circuit, comprising:

an instruction decode unit, configured to decode a load instruction to generate a decoding result;
an instruction detector, coupled to the instruction decode unit, the instruction detector being configured to generate an indication signal by detecting if the load instruction is in a load-use scenario;
an address generator, coupled to the instruction decode unit, the address generator being configured to generate a first address requested by the load instruction according to the decoding result;
and
a data buffer, coupled to the instruction detector and the address generator, the data buffer being configured to selectively store the first address generated from the address generator according to the indication signal, wherein when the indication signal indicates that the load instruction in the load-use scenario, the data buffer is configured to store the first address generated from the address generator, and store data requested by the load instruction according to the first address.

2 more elements

A data processing method, comprising:

receiving a load instruction, and generating an indication signal by detecting if the load instruction is in a load-use scenario;
decoding the load instruction to generate a decoding result;
generating a first address requested by the load instruction according to the decoding result;
selectively storing the first address according to the indication signal, wherein when the indication signal indicates that the load instruction is in the load-use scenario, storing the first address into a data buffer;
and
when the indication signal indicates that the load instruction is in the load-use scenario, storing data requested by the load instruction into the data buffer according to the first address.

3 more elements

Dependencies are inferred from the claim text.

Processor circuit and data processing method

Life of this patent

Processor circuit and data processing method

Life of this patent

Abstract

Claims20