Implementing a read setup in 3D NAND flash memory to reduce voltage threshold deviation over time

A memory controller for controlling a memory including a memory array, comprising a plurality of blocks, the memory controller comprising:

• control circuits comprising logic to execute operations comprising:
• in response to an access of a block of memory:
• updating a first queue to identify the accessed block of memory in response to a determination that the accessed block of memory is not already identified in the first queue and a determination that the accessed block of memory is not already identified in a second queue;
• and
• updating the second queue to identify the accessed block of memory in response to a determination that the accessed block of memory is already identified in the first queue;
• scanning the second queue to identify, as a read setup candidate, each block of the memory that is identified as present in the second queue longer than a predetermined threshold;
• and
• performing a read setup operation on a block of the memory that has been identified as the read setup candidate.

A method of operating a memory, the method comprising:

• maintaining a read setup permitted list to identify blocks of the memory in dependence upon their use;
• in response to an access of a block of the memory:
• determining that the accessed block of the memory is included in the read setup permitted list;
• and
• in response to the determination that the accessed block is included in the read setup permitted list, identifying the accessed block of the memory as a read setup candidate;
• and
• performing a read setup operation on the accessed block of the memory that has been identified as the read setup candidate.