Memory controller and method performed by the memory controller
AssigneeCanon Kabushiki Kaisha
InventorKohei Murayama
Life of this patent
Estimating the term…
Abstract
A memory controller is capable of issuing a first write command for writing data of a predetermined size in a DRAM, and a second write command for writing data of a size smaller than the predetermined size in the DRAM. The memory controller comprises a receiving unit configured to receive a request to the DRAM from a bus; a determining unit configured to determine whether a command that is after the second write command when a reception sequence of a request is observed is issuable in a period until the second write command is issued after a preceding command is issued; and an issuing unit configured to issue a command determined to be issuable before the second write command.
Claims13
A memory controller having a function of issuing a first write command for writing data of a predetermined size in a DRAM, and a second write command for writing data of a size smaller than the predetermined size in the DRAM, a penalty of the second write command being longer than a penalty of the first write command, the memory controller comprising:
- a receiving unit configured to receive a writing request to the DRAM from a bus;
- a determining unit configured to determine that a third command which is subsequent to the second write command in a sequence of commands in the received writing request is issuable in a period until the second write command is issued after a preceding command is issued, based on a length of a penalty of the third command and a length of the penalty of the second write command;
- and
- an issuing unit configured to issue the third command determined to be issuable before the second write command.
A method that is performed by a memory controller, the memory controller having a function of issuing a first write command for writing data of a predetermined size in a DRAM, and a second write command for writing data of a size smaller than the predetermined size in the DRAM, a penalty of the second write command being longer than a penalty of the first write command, the method comprising:
- receiving a writing request to the DRAM from a bus;
- determining that a third command which is subsequent to the second write command in a sequence of commands in the received writing request is issuable in a period until the second write command is issued after a preceding command is issued, based on a length of a penalty of the third command and a length of the penalty of the second write command;
- and
- issuing the third command determined to be issuable before the second write command.
A method that is performed by a memory controller configured to control a DRAM complying with LPDDR4, the method comprising issuing, in a period until a Masked Write command to a certain bank is issued after a Write command to the certain bank is issued, a Write command to another bank.
Dependencies are inferred from the claim text.