Memory controller for non-interfering accesses to nonvolatile memory by different masters, and related systems and methods

A method, comprising:

• assigning different nonvolatile memory (NVM) banks to different control processes of a controller device according to core assignment data, each control process issuing access requests only to an assigned NVM bank;
• storing time division multiplexer (TDM) assignment data that assigns each of a plurality of TDM command slots to one of the control processes in a predetermined order, without more than one control process being assigned to the same TDM command slot;
• multiplexing access requests from the control processes into a sequence of command slots according to the TDM assignment data and the core assignment data;
• by operation of a memory controller circuit of the controller device;
• generating command and address data from access requests received from the MUX during the assigned TDM command slots on a unidirectional command-address bus, and
• receiving read data on a unidirectional parallel data bus in synchronism with rising and falling edges of a received data clock, the read data being received in TDM read slots having the predetermined order assigned by the TDM assignment data;
• and
• demultiplexing the read data from each TDM read slot to the one of the control processes based on the TDM read slot position in the predetermined order.

A system, comprising:

• a processor device that includes
• a plurality of processor cores,
• memory circuits configured to store
• time division multiplexer (TDM) assignment data that assigns each of a plurality of TDM command slots to one of the processor cores in a predetermined order, without more than one processor being assigned to the same TDM command slot, and
• core assignment data that assigns the same processing cores to different nonvolatile memory (NVM) banks,
• a multiplexer (MUX) configured to order read requests from the processor cores into a sequence of command slots according to the TDM assignment data and the core assignment data,
• a memory controller configured to:
• generate NVM command and address data in response to the read requests from the MUX, and
• receive read data in TDM read slots having the predetermined order established by the TDM assignment data, and
• a demultiplexer (DMUX) configured to provide the read data of each TDM read slot to one of the processor cores;
• a NVM device that includes a plurality of separately addressable banks;
• a unidirectional command-address bus configured to transmit the command and address data from the processor device to the NVM device;
• and
• a unidirectional data bus configured to transmit the read data from the NVM device to the processor device.