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US 11,385,808 B2Granted
Memory performing defragmentation operation using data collecting area and method of operating the same
AssigneeSK hynix Inc.
InventorDa Hoo Kim
Life of this patent
Estimating the term…
Abstract
A method of operating a memory comprises reading a first node including first data and a first link; writing the first data to a data collecting area; updating a first collecting link of the first data, which is written in the data collecting area to a position in the data collecting area; reading a second node corresponding to the first link, the second node including second data and a second link; and writing the second data to a position in the data collecting area, which is designated by the first collecting link.
Claims16
A method of operating a memory, the method comprising:
- reading a first node including first data and a first link;
- writing the first data to a data collecting area;
- updating a first collecting link of the first data, which is written in the data collecting area to a position in the data collecting area;
- reading a second node corresponding to the first link, the second node including second data and a second link;
- and
- writing the second data to a position in the data collecting area, which is designated by the first collecting link.
3 more elements
A memory, comprising:
- a normal area including a plurality of memory cells;
- a data collecting area including a plurality of memory cells;
- and
- a defragmentation circuit reading a plurality of data linked from the normal area, writing the plurality of data to the data collecting area, and controlling the normal area and the data collecting area to update links to enable the plurality of data written to the data collecting area to be linked in the data collecting area,
- wherein the defragmentation circuit:
- reads a first node from the normal area, the first node including first data and a first link;
- writes the first data to the data collecting area;
- updates a first collecting link of the first data, which is written in the data collecting area to a position in the data collecting area;
- reads a second node corresponding to the first link from the normal area, the second node including second data and a second link;
- and
- writes the second data to a position designated by the first collecting link in the data collecting area.
8 more elements
A memory, comprising:
- a normal area including a plurality of memory cells;
- a data collecting area including a plurality of memory cells;
- and
- a defragmentation circuit reading a plurality of data linked from the normal area, writing the plurality of data to the data collecting area, and controlling the normal area and the data collecting area to update links to enable the plurality of data written to the data collecting area to be linked in the data collecting area,
- wherein the defragmentation circuit includes:
- a register circuit for storing information related to a defragmentation operation;
- an address translator for translating a link read from the normal area to a memory address;
- and
- a controller for controlling the defragmentation operation.
6 more elements
A memory comprising:
- a memory cell array including a normal area and a data collecting area, the normal area storing multiple dispersed nodes including a first node and a second node, the first node being linked to the second node, a size of the data collecting being less than that of the normal area;
- and
- a circuit configured to read data of the first node from the normal area, write the data of the first node in a first region of the data collecting area, link the first region to a second region adjacent to the first region, read data of the second node from the normal area and write the data of the second node in the second region.
Dependencies are inferred from the claim text.