US 11,385,795 B2 · Method and apparatus to enable individual non volatile memory express (NVMe) input/output (IO) queues on differing network addresses of an NVMe controller

Abstract

Methods and apparatus related to enabling individual NVMe (Non-Volatile Memory express) IO (Input Output or I/O) queues on differing network addresses of an NVMe controller are described. In one embodiment, a plurality of backend controller logic is coupled to a plurality of non-volatile memory devices. One or more virtual controller target logic (coupled to the plurality of backend controller logic) transmit data from a first portion of a plurality of IO queues to a first backend controller logic of the plurality of the backend controller logic. The one or more virtual controller target logic transmit data from a second portion of the plurality of IO queues to a second backend controller logic of the plurality of backend controller logic. Other embodiments are also disclosed and claimed.

Claims20

Dependent claims

An apparatus comprising:

at least one processor to:
execute an operating system (OS), wherein the OS is to provide support for access to at least one Non-Volatile Memory express (NVMe) compatible target device, wherein the NVMe compatible target device is to operate consistent at least with a Non-Volatile Memory Express Specification and wherein the at least one NVMe compatible target device provides access to at least one admin queue and at least one input output (IO) queue,
use an NVMe host node to communicate with an NVMe compatible target device, and
process a request from a requester to communicate with the NVMe compatible target device;
and
an interface to transmit the request in at least one Ethernet packet to a target device associated with the NVMe compatible target device.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/381,994Filed 11 Apr 2019 · continuation

Priority

21 Dec 2015

Published

US 2019/0303003 A13 Oct 2019

Granted

12 Jul 2022

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 3/061
Specifically adapted to achieve a particular effect: improving I/O performance
G06F 3/0655
Making use of a particular technique: vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more…
G06F 3/0656
Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices: data buffering…
G06F 3/0688
Plurality of storage devices: non-volatile semiconductor memory arrays

Family

Application14/976,949Parent of this continuation · filed 21 Dec 2015

US 2019/0303003 A1Pre-grant publication · published 3 Oct 2019

US 10,275,160 B2Parent of this continuation

US 2017/0177216 A1Published application

US 11,385,795 B2This patent

From the US filing history. Foreign family members aren’t listed.

Method and apparatus to enable individual non volatile memory express (NVMe) input/output (IO) queues on differing network addresses of an NVMe controller

Life of this patent

Method and apparatus to enable individual non volatile memory express (NVMe) input/output (IO) queues on differing network addresses of an NVMe controller

Life of this patent

Abstract

Claims20