Ultra-low power neuromorphic artificial intelligence computing accelerator
AssigneeQUALCOMM Incorporated
InventorsYu Pu, Yang Du
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Abstract
A three-dimensional (3D) ultra-low power neuromorphic accelerator is described. The 3D ultra-low power neuromorphic accelerator includes a power manager as well as multiple tiers. The 3D ultra-low power neuromorphic accelerator also includes multiple cores defined on each tier and coupled to the power manager. Each core includes at least a processing element, a non-volatile memory, and a communications module.
Claims11
A three-dimensional (3D) asynchronous network-on-chip (3D ANOC) architecture, comprising:
- a 3D ultra-low power neuromorphic accelerator integrated into the 3D ANOC architecture, the 3D ultra-low power neuromorphic accelerator comprising:
- a power manager;
- a plurality of tiers;
- and
- a plurality of cores defined on each tier and coupled to the power manager, each core comprising at least:
- a processing element;
- a non-volatile memory;
- and
- a communications module.
A 3D ultra-low power neuromorphic accelerator, comprising:
- a power manager;
- a plurality of tiers;
- and
- a plurality of cores defined on each tier and coupled to the power manager, each core comprising at least:
- a processing element;
- a non-volatile memory;
- and
- a communications module, in which each of the plurality of cores is locally synchronous and globally asynchronous.
A 3D ultra-low power neuromorphic accelerator, comprising:
- a power manager;
- a plurality of tiers;
- and
- a plurality of cores defined on each tier and coupled to the power manager, each core comprising at least:
- a processing element;
- a non-volatile memory;
- and
- a communications module, in which the power manager determines a power state of each of the plurality of cores based on a probabilistic approximation.
A 3D ultra-low power neuromorphic accelerator, comprising:
- a power manager;
- a plurality of tiers;
- and
- a plurality of cores defined on each tier and coupled to the power manager, each core comprising at least:
- a processing element;
- a non-volatile memory;
- and
- a communications module, in which the tiers are of different processing nodes.
Dependencies are inferred from the claim text.