Multi-chip system, chip, and clock synchronization method
AssigneeRealtek Semiconductor Corp.
InventorPing-I Chang
Life of this patent
Estimating the term…
Abstract
A multi-chip system includes a first chip and a second chip. The first chip is configured to generate a first symbol clock signal according to a first clock signal from a first oscillator. The second chip is configured to generate a second symbol clock signal according a second clock signal from a second oscillator, detect a difference between the second symbol clock signal and the first symbol clock signal to generate an error signal, and synchronize the first symbol clock signal and the second symbol clock signal according to the error signal.
Claims20
A multi-chip system, comprising:
- a first chip configured to generate a first symbol clock signal according to a first clock signal from a first oscillator;
- and
- a second chip configured to generate a second symbol clock signal and a system clock signal according to a second clock signal from a second oscillator, start counting at least one pulse of the system clock signal according to one of the first symbol clock signal and the second symbol clock signal, and stop counting the at least one pulse according to another one of the first symbol clock signal and the second symbol clock signal to generate an error signal, and synchronize the first symbol clock signal and the second symbol clock signal according to the error signal.
A chip, comprising:
- a synchronization circuitry configured to detect a difference between a first symbol clock signal and a second symbol clock signal to generate an error signal, wherein the first symbol clock signal is generated by a master chip according to a first clock signal from a first oscillator;
- a sampling clock generator circuit configured to generate a sampling clock signal according to a second clock signal from a second oscillator and the error signal;
- and
- a symbol clock generator circuit configured to generate the second symbol clock signal that is synchronized with the first symbol clock signal according to the sampling clock signal.
A clock synchronization method, comprising:
- receiving a first symbol clock signal from a master chip, wherein the master chip is configured to generate the first symbol clock signal according to a first clock signal from a first oscillator;
- generating a second symbol clock signal and a system clock signal according to a second clock signal from a second oscillator;
- and
- starting counting at least one pulse of the system clock signal according to one of the first symbol clock signal and the second symbol clock signal and stopping counting the at least one pulse according to another one of the first symbol clock signal and the second symbol clock signal to generate an error signal, in order to adjust the second symbol clock signal according to the error signal to synchronize the second symbol clock signal with the first symbol clock signal.
Dependencies are inferred from the claim text.