Clock distribution circuit and semiconductor device including the clock distribution circuit

A clock distribution circuit comprising:

• a data clock generation circuit configured to be input a power source voltage and configured to generate an internal clock signal according to an external clock signal;
• and
• a global distribution circuit includes a first circuit and a second circuit coupled to a global line, configured to receive the internal clock signal through the first circuit and distribute the internal clock signal to an exterior of the clock distribution circuit through the second circuit,
• wherein the first circuit is configured to be input with a first bias voltage and the power source voltage and the second circuit is configured to be input with a second bias voltage and the power source voltage, and
• wherein a level of the first bias voltage and a level of the second bias voltage are controlled independently of each other.