Back to results
US 11,385,673 B1Granted
Digital data processing circuitry
OwnerDavid James Ellisinventor
Life of this patent
Estimating the term…
Abstract
Digital data processing circuitry is described that uses combinatorial logic hardware and sequential logic hardware to process one or more inputs. For each input a periodic sequence is generated that is based at least in part on a value of the input and a weight value. A match is determined at an event time when the periodic sequence(s) matches a corresponding arbitrary reference pattern. The digital data processing circuitry may be implemented as an integrated circuit as part of an interconnected network of devices that may be trained and subsequently used for recognition or other complex data processing tasks.
Claims6
An apparatus comprising:
- a master counter circuit configured to:
- generate a master count value that is indicative of a master cycle window;
- and
- generate a reset signal responsive to the master count value being greater than or equal to a maximum value;
- one or more trip weight circuits, wherein each trip weight circuit is configured to:
- accept an input signal representative of data expressed as input values comprising a first number of binary bits;
- accept a weight value associated with the input values;
- generate a first half of a period of a waveform by:
- setting a first level of the waveform to the input values;
- initiating a weight counter that counts from a start value to an end value specified by the weight value;
- and
- generating, for each count of the weight counter, a first output at the first level;
- generate a second half of the period of the waveform by:
- determining the weight counter has reached the end value;
- and
- setting a second level of the waveform by inverting the input values;
- wherein the waveform is a continuous square wave having a frequency based on the weight value;
- generate, for each count of the weight counter, a second output at the second level;
- and
- reset the weight counter responsive to the reset signal;
- one or more transform event circuits, wherein each transform event circuit is configured to:
- accept the waveform from a corresponding trip weight circuit;
- compare a value of the waveform at a given time to a reference pattern, wherein the reference pattern consists of a second number of binary bits, further wherein the first number of binary bits of the input signal is equal to the second number of binary bits in the reference pattern;
- and
- generate a found signal indicative of a match between the values of the waveform and the reference pattern;
- and
- an output circuit, wherein the output circuit is configured to:
- receive found signals from each of the one or more transform event circuits;
- determine an event time indicative of a value of the master counter circuit contemporaneous to receiving the found signals;
- determine the event time is less than a threshold value;
- generate an output signal indicative of the match;
- and
- clear an event timer responsive to the reset signal.
30 more elements
An apparatus comprising:
- a master counter circuit configured to:
- generate a master count value;
- and
- generate a reset signal responsive to the master count value being greater than or equal to a maximum value;
- one or more trip weight circuits, wherein each trip weight circuit is configured to:
- accept an input value comprising a first number of binary bits;
- accept a weight value associated with the input value;
- generate a waveform based at least in part on the input value and the weight value, wherein the waveform is a square wave having a frequency based on the weight value;
- and
- reset a counter responsive to the reset signal;
- one or more transform event circuits, wherein each transform event circuit is configured to:
- accept the waveform from a corresponding trip weight circuit;
- compare a value of the waveform at a given time to a reference pattern, wherein the reference pattern comprises a second number of binary bits and the first number of binary bits is equal to the second number of binary bits;
- and
- generate a found signal indicative of a match between the value of the waveform and the reference pattern;
- and
- an output circuit, wherein the output circuit is configured to:
- accept found signals from each of the one or more transform event circuits;
- determine an event time, wherein the event time is based at least in part on the master count value;
- determine the event time is less than a threshold value;
- responsive to the found signals from each of the one or more transform event circuits, generate an output signal indicative of a match;
- and
- responsive to the reset signal, clear an event timer.
20 more elements
A method implemented in an integrated circuit, the method comprising:
- receiving one or more inputs, wherein the one or more inputs comprise a first sequence of bits;
- generating, for each input, a time-varying periodic sequence having a first portion and a second portion, wherein:
- the time-varying periodic sequence comprises a square wave with a frequency based on a weight value;
- the first portion comprises a first level corresponding to an individual input, the first level having a first duration that is based on the weight value;
- and
- the second portion comprises a second level corresponding to an inverted value of the individual input, the second level having a second duration that is based on the weight value;
- determining, at an event time, a value of the time-varying periodic sequence of each input matches a corresponding reference pattern comprising a second sequence of bits;
- determining the event time is less than or equal to a threshold value;
- and
- generating an output signal indicative of a match between the one or more inputs and the reference pattern.
7 more elements
Dependencies are inferred from the claim text.