Reference voltage generating circuit and low power consumption sensor
AssigneeNational Yang Ming Chiao Tung University
InventorsYu-Te Liao, Cheng-Ze Shao, Shih-Che Kuo
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AssigneeNational Yang Ming Chiao Tung University
InventorsYu-Te Liao, Cheng-Ze Shao, Shih-Che Kuo
Estimating the term…
A low-power CMOS reference voltage generating with enhanced power supply rejection ratio (PSRR) and fast start-up time is disclosed. The reference voltage generating is generated by the stacked diode-connected MOS transistors (SDMT) architecture to reduce the dependence on process, voltage and temperature. The self-biased and capacitor coupled architecture can shorten the start-up time without increasing power consumption and improve the bandwidth of the power supply rejection ratio. This design is implemented using a CMOS process, which can achieve stabilization time of 0.2 ms. Under the same power consumption, this design is 274 times better than a design without a start-up time enhancement. The power supply rejection ratio measured at 100 Hz is −73.5 dB. In the temperature range of −40 to 130° C., the average temperature coefficient is 62 ppm/° C.
A self-biased and capacitive-coupled reference voltage generating circuit, comprising:
A reference voltage generating circuit with a stacked diode-connected architecture, comprising:
Dependencies are inferred from the claim text.