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US 11,381,425 B2Granted
Semiconductor device and memory system
AssigneeKioxia Corporation
InventorsKensuke Yamamoto, Kosuke Yanagidaira
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a first chip and a second chip. The first chip includes a first circuit having a first output terminal. The second chip includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line. When the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal.
Claims18
A semiconductor system comprising:
- a first memory device that includes
- a first memory core configured to store data,
- a first input/output terminal, and
- a first circuit configured to calibrate an output impedance at the first input/output terminal;
- a second memory device that includes
- a second memory core configured to store data,
- a second input/output terminal connected to the first input/output terminal, and
- a second circuit configured to calibrate an output impedance at the second input/output terminal;
- a third memory device that includes
- a third memory core configured to store data,
- a third input/output terminal connected to the first and second input/output terminals, and
- a third circuit configured to calibrate an output impedance at the third input/output terminal;
- a fourth memory device that includes
- a fourth memory core configured to store data,
- a fourth input/output terminal connected to the first to third input/output terminals, and
- a fourth circuit configured to calibrate an output impedance at the fourth input/output terminal;
- and
- a controller that includes a fifth input/output terminal connected to the first to fourth input/output terminals and is configured to output from the fifth input/output terminal a calibration command for calibrating an output impedance, wherein
- after the controller outputs a first calibration command including an address of the first memory device, the first circuit of the first memory device starts a first calibration operation to calibrate the output impedance at the first input/output terminal while issuing a signal indicating that the first memory device is in a busy state, and upon elapse of a first period from when the first calibration operation has started, terminates the first calibration while issuing a signal indicating that the first memory device is in a ready state,
- after the controller outputs a second calibration command including at least one of addresses of the second to fourth memory devices after the first calibration command is output, the second circuit of the second memory device starts a second calibration operation to calibrate the output impedance at the second input/output terminal while issuing a signal indicating that the second memory device is in the busy state, and upon elapse of a second period from when the second calibration operation has started, terminates the second calibration while issuing a signal indicating that the second memory device is in the ready state, and
- the second period is shorter than the first period.
18 more elements
Dependencies are inferred from the claim text.