Decode device

A decode device comprising:

• a dividing circuit configured to divide a first bit string including variable length symbols into a plurality of second bit strings and to output the divided second bit strings;
• and
• a first decode circuit configured to decode the plurality of second bit strings, wherein
• the dividing circuit includes:
• a first block configured to execute first operation which includes
• acquiring a third bit string which is a part of the first bit string,
• calculating a head bit of a symbol succeeding one symbol by assuming one bit to be a head of the one symbol, and
• recording the head bit as boundary information associated with the one bit,
• the first block executing the first operation for each bit of at least a part of the third bit string;
• a second block configured to execute second operation which includes
• overwriting boundary information associated with one bit with boundary information associated with a bit indicated by the boundary information associated with the one bit,
• the second block executing the second operation for each bit of at least a part of the third bit string for a set number of times;
• and
• a third block configured to output a fourth bit string starting with a first bit of the third bit string and ending with one bit before a second bit indicated by boundary information associated with a first bit of the third bit string, as one of the plurality of second bit strings.