US 11,381,245 B1 · Clock step control circuit and method thereof

Abstract

The disclosure provides a clock step control circuit and a method thereof. The clock step control circuit includes a clock divider, a multiplexer, and a controller. The clock divider receives a first clock signal and outputs multiple second clock signals. The multiplexer receives the second clock signals and outputs one of the second clock signals. The controller is coupled to the clock divider and the multiplexer. When the controller receives an interrupt signal, the controller outputs a selection signal to the multiplexer according to the interrupt signal. The multiplexer outputs another one of the second clock signals according to the selection signal. The clock step control circuit and the method thereof in the disclosure can appropriately switch the clock signal to output a clock signal with an appropriate clock frequency.

Claims18

Dependent claims

A clock step control circuit, comprising:

a clock divider, receiving a first clock signal and outputting a plurality of second clock signals;
a multiplexer, receiving the plurality of the second clock signals and outputting one of the plurality of the second clock signals;
and
a controller, coupled to the clock divider and the multiplexer,
wherein, when the controller receives an interrupt signal, the controller outputs a selection signal to the multiplexer according to the interrupt signal, and the multiplexer outputs another one of the plurality of the second clock signals according to the selection signal,
wherein the plurality of the second clock signals comprise different clock frequencies, and
when the controller receives the interrupt signal, the multiplexer sequentially outputs at least part of the plurality of the second clock signals in a form of multi-step changing from high clock frequency to low clock frequency.

4 more elements

A clock step control method, comprising:

receiving a first clock signal through a clock divider and outputting a plurality of second clock signals;
receiving the plurality of the second clock signals through a multiplexer and outputting one of the plurality of the second clock signals;
wherein, outputting a selection signal to the multiplexer according to an interrupt signal through a controller when the controller receives the interrupt signal;
and
outputting another one of the plurality of the second clock signals according to the selection signal through the multiplexer,
wherein the plurality of the second clock signals comprises different clock frequencies, and the step of outputting the another one of the plurality of the second clock signals according to the selection signal through the multiplexer comprises:
sequentially outputting at least part of the plurality of the second clock signals in a form of multi-step changing from high clock frequency to low clock frequency through the multiplexer.

4 more elements

Dependencies are inferred from the claim text.

Clock step control circuit and method thereof

Life of this patent

Clock step control circuit and method thereof

Life of this patent

Abstract

Claims18