Duty cycle correction method and circuit thereof

A Duty Cycle Correction circuit for a transceiver, comprising:

• a delay-line comprising a plurality of delay components, driven by an input signal and configured to generate a plurality of delayed input signals, each said delayed input signal is delayed by at least a unit delay;
• first logic, controlled by a first control signal, configured to receive the plurality of delay-signals and configured to select at least one of the delayed-signal as a first signal;
• a plurality of duty scaling components comprising one or more of an incrementing component configured to generate at least an incremented duty signal (Path1) when a Duty Cycle of the input signal is less than the ideal duty cycle and a decrementing component configured to generate a decremented duty signal (Path2) when the Duty cycle of the input signal is more than the ideal Duty Cycle, based on the selected delayed signals and the input signal;
• path correction logic configured to generate a corrected duty cycle based on the selection of at least one of:
• the incremented duty cycle or decremented duty cycle by providing a second control signal, wherein the increment or decrement in duty cycle is performed until the detected duty cycle of the input signal remains lesser or greater than a threshold level.

A Duty Cycle Correction (DCC) circuit for a transceiver, comprising:

• processing circuitry configured to:
• generate a plurality of delayed input signals, each said delayed input signal is delayed by at least a unit delay;
• receive the plurality of delay-signals to select at least one of the delayed-signal as a first signal;
• generate an incremented duty signal (Path1) when a Duty Cycle of the input signal is less than an ideal duty cycle and a decremented duty signal (Path2) when the Duty cycle of the input signal is more than the ideal Duty Cycle, based on the first signal and the input signal;
• generate a corrected duty cycle based on the selection of at least one of:
• the incremented duty cycle or decremented duty cycle by providing a second control signal, wherein the increment or decrement in duty cycle is performed until the detected duty cycle of the input signal remains lesser or greater than a threshold level.