Digital measurement circuit and memory system using the same
AssigneeSamsung Electronics Co., Ltd.
InventorsKwan Yeob Chae, Jong-Ryun Choi
Life of this patent
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Abstract
A digital measurement circuit includes a first input flip-flop which receives a first signal through a data input terminal, receives a first clock signal through a clock input terminal, and outputs a second signal; a second input flip-flop which receives the second signal through a data input terminal, receives a second clock signal, which is an inverted signal of the first clock signal, through a clock input terminal, and outputs a third signal; and a delay line which receives the second signal and outputs first through n-th output signals, wherein n is an integer greater than one, and the first through n-th output signals are sampled based on the third signal to output first through n-th sampling signals is provided.
Claims19
A duty measurement circuit comprising:
- a first flip-flop configured to receive an enable signal and a clock signal, and to output a first output signal;
- a second flip-flop configured to receive the first output signal and an inverted clock signal, and to output a second output signal;
- an inverter including an input terminal directly connected to an input of the first flip-flop and configured to receive the clock signal, and an output terminal directly connected to an input of the second flip-flop and configured to output the inverted clock signal;
- a delay line configured to delay the first output signal, and output a plurality of delayed signals by delaying the first output signal;
- and
- wherein at least one of a high or low pulse width of the clock signal is substantially equal to a difference between a rising time of the first output signal and a rising time of the second output signal.
A method comprising:
- receiving an enable signal and a clock signal;
- generating a first signal by providing the enable signal and the clock signal to a first flip-flop;
- inverting the clock signal to generate an inverted clock signal;
- generating a second signal by providing the first signal and the inverted clock signal to a second flip-flop;
- delaying the first signal to generate a plurality of delayed signals;
- and
- measuring a high pulse width of the clock signal based on the plurality of delayed signals;
- wherein at least one of a high or low pulse width of the clock signal is substantially equal to a difference between a rising time of the first signal and a rising time of the second signal.
A memory system comprising:
- a memory cell array configured to store data;
- an input/output driver configured to read the data stored in the memory cell array or write data to the memory cell array;
- a phase-locked loop configured to receive a clock signal and adjust the clock signal;
- duty adjusting circuitry configured to receive the adjusted clock signal from the phase-locked loop and adjust a duty of the adjusted clock signal based on a control signal;
- duty measuring circuitry configured to,
- receive an external signal according to at least one of the duty adjusted clock signal from the duty adjusting circuitry or a data strobe from the input/output driver,
- generate a first internal signal and a second internal signal based on the external signal, and
- delay the external signal to generate a plurality of delayed signals;
- and
- duty control circuitry configured to receive the plurality of delayed signals, calculate a duty error of a pulse width of the duty adjusted clock signal or the data strobe based on the plurality of delayed signals, and generate the control signal based on the calculated duty error, wherein
- the duty measuring circuitry includes,
- a first flip-flop configured to receive the external signal, and to output the first internal signal,
- a second flip-flop configured to receive the first internal signal, and to output the second internal signal, and
- wherein at least one of a high or low pulse width of the clock signal is substantially equal to a difference between a rising time of the first internal signal and a rising time of the second internal signal.
Dependencies are inferred from the claim text.