Continuous time linear equalization system and method
AssigneeCadence Design Systems, Inc.
InventorsClarence Kar Lun Tam, Guillaume Fortin
Life of this patent
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Abstract
The present disclosure relates to an apparatus and method for continuous time linear equalization. Embodiments include a differential amplifier including a first transistor and a second transistor, wherein the differential amplifier includes a peak-generating path and a peak-reduction path. Embodiments also include at least one switch and at least one capacitor located between a source and a drain of at least one of the first transistor and the second transistor to create a capacitive path between the source and drain, wherein the at least one switch and at least one capacitor are configured to reduce bandwidth.
Claims16
A continuous time linear equalization circuit, comprising:
- a differential amplifier including a first transistor and a second transistor, wherein the differential amplifier includes a peak-generating path and a peak-reduction path;
- and
- at least one switch and at least one capacitor located between a source and a drain of at least one of the first transistor and the second transistor to create a capacitive path between the source and drain, wherein the at least one switch and at least one capacitor are configured to reduce bandwidth, wherein the at least one switch and the at least one capacitor includes a first switch and a first capacitor located between a source and a drain of the first transistor and a second switch and a second capacitor located between a source and a drain of the second transistor;
- and
- a source degenerated capacitor array that is connected in a peak generation mode and disconnected in a peak reduction mode.
A method for continuous time linear equalization, comprising:
- providing a differential amplifier including a first transistor and a second transistor, wherein the differential amplifier includes a peak-generating path and a peak-reduction path;
- reducing high frequency peaking using a first switch and a first capacitor located between a source and a drain of the first transistor and a second switch and a second capacitor located between a source and a drain of the second transistor to create a capacitive path between the source and drain;
- and
- connecting a source degenerated capacitor array in a peak generation mode or disconnecting the source degenerated capacitor array in a peak reduction mode.
A method for continuous time linear equalization, comprising:
- providing a differential amplifier including a first transistor and a second transistor, wherein the differential amplifier includes a peak-generating path and a peak-reduction path;
- reducing high frequency peaking using at least one switch and at least one capacitor located between a source and a drain of the first transistor;
- enabling N of the at least one capacitor and each of the at least one switch in a peak reduction position during maximum peak reduction, wherein N is a maximum number of capacitors;
- and
- enabling one of the at least one capacitor and each of the at least one switch in a peak generation position.
Dependencies are inferred from the claim text.