Apparatus and method for an analog to digital converter
AssigneeSTMicroelectronics International N.V.
InventorRiju Biswas
Life of this patent
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Abstract
An apparatus includes a load pair including a first transistor and a second transistor, a common mode feedback circuit comprising a first common mode feedback transistor and a second common mode feedback transistor, wherein a drain of the first common mode feedback transistor is coupled to a source of the first transistor, and a gate of the first common mode feedback transistor is coupled to a drain of the first transistor, and a drain of the second common mode feedback transistor is coupled to a source of the second transistor, and a gate of the second common mode feedback transistor is coupled to a drain of the second transistor, and an offset cancellation stage coupled to outputs of the load pair.
Claims20
An amplifier comprising:
- a load pair including a first transistor and a second transistor;
- a common mode feedback circuit comprising a first common mode feedback transistor and a second common mode feedback transistor, wherein:
- a drain of the first common mode feedback transistor is coupled to a source of the first transistor, and a gate of the first common mode feedback transistor is coupled to a drain of the first transistor;
- and
- a drain of the second common mode feedback transistor is coupled to a source of the second transistor, and a gate of the second common mode feedback transistor is coupled to a drain of the second transistor;
- and
- a cross-coupled transistor pair configured to boost a gain of the amplifier, wherein the cross-coupled transistor pair is connected between a gate of the first transistor and a gate of the second transistor.
A method comprising:
- configuring an amplifier to operate in an offset cancellation phase to generate a first offset voltage at a first output of the amplifier and a second offset voltage at a second output of the amplifier, and store the first offset voltage and the second offset voltage at a first storage element and a second storage element respectively, wherein the first storage element is coupled to the first output of the amplifier through a first auxiliary switch, and the second storage element is coupled to the second output of the amplifier through a second auxiliary switch;
- configuring the amplifier to operate in a reset phase through turning on a first reset switch coupled between the first output and the second output of the amplifier;
- and
- configuring the amplifier to operate in an amplification phase, wherein in the amplification phase, a first offset-cancellation voltage and a second offset-cancellation voltage are fed into the first output and the second output of the amplifier, respectively.
An apparatus comprising:
- a load pair including a first transistor and a second transistor;
- a common mode feedback circuit comprising a first common mode feedback transistor and a second common mode feedback transistor, wherein:
- a drain of the first common mode feedback transistor is coupled to a source of the first transistor, and a gate of the first common mode feedback transistor is coupled to a drain of the first transistor;
- and
- a drain of the second common mode feedback transistor is coupled to a source of the second transistor, and a gate of the second common mode feedback transistor is coupled to a drain of the second transistor;
- and
- an offset cancellation stage coupled to outputs of the load pair.
Dependencies are inferred from the claim text.