Surge protection circuit

A method for operating a clamp circuit configured to protect a load against a surge, the method comprising:

• powering the clamp circuit including a power dissipation circuit including at least one transistor and a resistor;
• dissipating power, via the power dissipation circuit, from the surge across the resistor and the at least one transistor by turning on the at least one transistor, wherein when the at least one transistor is turned on, a voltage divider is formed between a source impedance and the resistor of the power dissipation circuit disposed in series with a channel of the at least one transistor and the resistor holds a portion of transient pulse seen by the load to a low voltage and the low voltage is added to a threshold voltage of the at least one transistor;
• enabling via a sub-circuit of the clamp circuit, a built-in test function of the clamp circuit by applying a test pulse signal to a gate of the at least one transistor, the test pulse signal being a digital signal, and asserting a digital response signal at an output terminal of the clamp circuit using a readout circuit including a readout circuit transistor, a first resistor connected between the at least one transistor and the resistor of the power dissipation circuit, and a second resistor and a diode;
• and
• determining, in response to enabling the built-in test function, a status of the clamp circuit.

A built-in test circuit to test the functionality of a clamp circuit comprising a power dissipation circuit including at least one transistor and a resistor, the built-in test circuit comprising:

• an output terminal;
• an input terminal configured to receive an input signal for activating the built-in test circuit and a test pulse signal, wherein the built-in test circuit is configured to apply the test pulse signal to a gate of the at least one transistor;
• and
• a readout circuit comprising:
• a first resistor connected between the at least one transistor and the resistor of the power dissipation circuit,
• a readout circuit transistor connected to the first resistor, and
• a second resistor and diode connected in series with the readout circuit transistor, wherein the diode is configured to output a test response signal at the output terminal, and when the clamp circuit is functional the test response signal is a replica of the test pulse signal.