Determining critical timing paths in a superconducting circuit design
AssigneeMicrosoft Technology Licensing, LLC
InventorsJanet L. Schneider, Paul Accisano, Mark G. Kupferschmidt, Kenneth Reneris
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Abstract
Systems and methods for determining critical timing paths in a superconducting circuit design including Josephson junctions are provided. An example method includes providing timing information concerning a plurality of source terminals of at least one logic gate coupled with a first sink terminal of the at least one logic gate. The method further includes using a processor, determining whether, in view of the timing information, the first sink terminal is reachable by a single flux quantum (SFQ) pulse within a predetermined range of arrival time based on an assigned first phase to the at least one logic gate.
Claims20
A method, implemented by a processor, for determining a critical timing path in a superconducting circuit design, wherein the superconducting circuit design comprises at least one logic gate including at least one Josephson junction, and wherein the at least one logic gate has an assigned first phase associated with a clock signal for clocking the at least one logic gate, the method comprising:
- providing timing information concerning a plurality of source terminals of the at least one logic gate coupled with a first sink terminal of the at least one logic gate;
- and
- using the processor, determining whether, in view of the timing information, the first sink terminal is reachable by a single flux quantum (SFQ) pulse within a predetermined range of arrival time based on the assigned first phase to the at least one logic gate.
A method, implemented by a processor, for determining a critical timing path in a superconducting circuit design, wherein the superconducting circuit design comprises a plurality of logic gates, and wherein each of the plurality of logic gates comprises at least one Josephson junction, the method comprising:
- providing timing information concerning a plurality of source terminals associated with the plurality of logic gates;
- receiving a selection of a first sink terminal from among a plurality of sink terminals associated with a target logic gate selected from among the plurality of logic gates;
- receiving an assignment of a phase to the target logic gate;
- and
- for each of the plurality of sink terminals:
- using the processor, determining whether each of the plurality of sink terminals is reachable by a respective single flux quantum (SFQ) pulse within a predetermined range of arrival time, and
- if the first sink terminal is not reachable within the predetermined range of arrival time, then inserting a Josephson transmission line (JTL) between a source terminal associated with the target logic gate and the first sink terminal determined to be unreachable within the predetermined range of arrival time, and upon determining that the first sink terminal is reachable, after an insertion of the JTL, within the predetermined range of arrival time, removing the first sink terminal from among the plurality of sink terminals as being associated with the critical timing path.
A system configured to determine a critical timing path in a superconducting circuit design, wherein the superconducting circuit design comprises at least one logic gate including at least one Josephson junction, and wherein the at least one logic gate has an assigned first phase associated with a clock signal for clocking the at least one logic gate, the system comprising:
- a first sub-system configured to provide timing information concerning a plurality of source terminals of the at least one logic gate coupled with a first sink terminal of the at least one logic gate;
- and
- a second sub-system, including a processor, configured to determine whether, in view of the timing information, the first sink terminal is reachable by a single flux quantum (SFQ) pulse within a predetermined range of arrival time based on the assigned first phase to the at least one logic gate.
Dependencies are inferred from the claim text.