Process to reduce plasma induced damage
AssigneeApplied Materials, Inc.
InventorsJianheng Li, Lai Zhao, Yujia Zhai, Soo Young Choi
Life of this patent
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Abstract
Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrode is disposed over the gate dielectric layer. The gate dielectric layer has a Dit of about 5e10 cm−2 eV−1 to about 5e11 cm−2 eV−1 and a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.
Claims12
A thin film transistor (TFT), comprising:
- a gate dielectric layer disposed on a semiconductor layer, the gate dielectric layer having a first surface and a second surface, the first surface contacts the semiconductor layer at an interface, the gate dielectric layer has a breakdown field between about 6 MV/cm and about 10 MV/cm, an interface trap density (Dit) of about 5e10 cm−2 eV−1 to about 5e11 cm−2 eV−1, and a hysteresis of about 0.10 V to about 0.30 V, the gate dielectric layer comprises:
- a thickness divided into a range of zones from the first surface corresponding to 0% of the thickness to the second surface corresponding to 100% of the thickness, each zone of the range of zones having a zone thickness and zone density;
- and
- a density profile through the range of zones having a minimum density and a maximum density, wherein:
- an initial zone of the range of zones adjacent to the first surface has the zone density with the minimum density;
- and
- a finial zone of the range of zones adjacent to the second surface has the zone density with the maximum density, the zone density of each zone disposed immediately over a prior zone is not less than the zone density of the prior zone.
A thin film transistor (TFT),
- comprising:
- a substrate;
- a buffer layer disposed on the substrate;
- a semiconductor layer disposed on the buffer layer;
- a gate dielectric layer disposed on the semiconductor layer, the gate dielectric layer having a first surface and a second surface, the first surface contacts the semiconductor layer at an interface, the gate dielectric layer has a breakdown field between about 6 MV/cm and about 10 MV/cm, an interface trap density (Dit) of about 5e10 cm−2 eV−1 to about 5e11 cm−2 eV−1, and a hysteresis of about 0.10 V to about 0.30 V, the gate dielectric layer comprises:
- a thickness divided into a range of zones from the first surface corresponding to 0% of the thickness to the second surface corresponding to 100% of the thickness, each zone of the range of zones having a zone thickness and zone density;
- and
- a density profile through the range of zones having a minimum density and a maximum density, wherein:
- an initial zone of the range of zones adjacent to the first surface has the zone density with the minimum density;
- and
- a finial zone of the range of zones adjacent to the second surface has the zone density with the maximum density, the zone density of each zone disposed immediately over a prior zone is not less than the zone density of the prior zone;
- a gate electrode disposed on the gate dielectric layer, the gate electrode contacting the second surface of the gate dielectric layer,
- an inter-layer dielectric (ILD) layer disposed on the gate dielectric layer and the gate electrode;
- and
- a source electrode disposed in a source electrode via of the ILD layer and a drain electrode is disposed in a drain electrode via of the ILD layer.
Dependencies are inferred from the claim text.