Top gate thin film transistor, fabricating method thereof, array substrate and display apparatus

A method for fabricating a thin film transistor, comprising:

• providing a substrate;
• forming an active layer comprising a first conducting region, a second conducting region, and a channel region between the first conducing region and the second conducting region;
• forming a gate on the active layer;
• forming an interlayer insulating layer covering the active layer and the gate;
• and
• forming a source and a drain on a side of the interlayer insulating layer opposite from the substrate,
• wherein the channel region includes a source side channel region, a drain side channel region, and a gate channel region, the source side channel region is between the first conducting region and the gate channel region, and the drain side channel region is between the second conducting region and the gate channel region;
• the thin film transistor is a single gate transistor;
• an orthographic projection of the gate on the substrate covers an orthographic projection of the gate channel region, an orthographic projection of the source side channel region and an orthographic projection of the drain side channel region are not covered by the gate on the substrate;
• a gate insulating layer is formed between the active layer and the gate, an orthographic projection of the gate insulating layer on the substrate covers the orthographic projection of the gate channel region, the orthographic projection of the source side channel region, and the orthographic projection of the drain side channel region, and an orthographic projection of the first conducting region and an orthographic projection of the second conducting region are not covered by the orthographic projection of the gate insulating layer on the substrate;
• a length of the orthographic projection of the gate insulating layer is greater than a length of the orthographic projection of the gate, and the length of the orthographic projection of the gate insulating layer is equal to a total length of the orthographic projection of the gate channel region, the orthographic projection of the source side channel region, and the orthographic projection of the drain side channel region;
• and
• the orthographic projection of the source fully covers the orthographic projection of the source side channel region, and the orthographic projection of the drain fully covers the orthographic projection of the drain side channel region.