Fin field-effect transistor device having hybrid work function layer stack

A method of forming a semiconductor device, the method comprising:

• forming a fin protruding above a substrate;
• forming dummy gate structures over the fin;
• surrounding the dummy gate structures with a dielectric layer;
• and
• replacing the dummy gate structures with metal gates, wherein the replacing comprises:
• removing the dummy gate structures to form a first gate trench, a second gate trench, and a third gate trench in the dielectric layer, wherein the third gate trench is between the first gate trench and the second gate trench;
• forming a first work function layer along sidewalls and a bottom of the first gate trench, and along a first sidewall and a first region of a bottom of the third gate trench;
• forming a second work function layer along sidewalls and a bottom of the second gate trench, and along a second sidewall and a second region of the bottom of the third gate trench, wherein a first sidewall of the first work function layer is at the bottom of the third gate trench and contacts a second sidewall of the second work function layer, wherein the first work function layer and the second work function layer are of a same type of work function layer;
• forming a third work function layer in the first gate trench, the second gate trench, and the third gate trench, wherein the third work function layer extends along and contacts the first work function layer and the second work function layer;
• and
• filling the first gate trench, the second gate trench, and the third gate trench with an electrically conductive material.

A method of forming a semiconductor device, the method comprising:

• forming a dummy gate structure over a first fin, a second fin, and a third fin that protrude above a substrate, wherein the third fin is between the first fin and the second fin;
• forming an interlayer dielectric (ILD) layer around the dummy gate structure;
• removing the dummy gate structure to form a recess in the ILD layer, wherein the recess exposes the first fin, the second fin, and the third fin;
• forming a gate dielectric layer in the recess over the first fin, the second fin, and the third fin;
• forming a first work function layer in the recess over and contacting the gate dielectric layer, wherein the first work function layer extends along first sidewalls and a first upper surface of the first fin;
• forming a second work function layer in the recess over and contacting the gate dielectric layer, wherein the second work function layer extends along second sidewalls and a second upper surface of the second fin, wherein the first work function layer extends along a first sidewall of the third fin and along a first portion of a third upper surface of the third fin, wherein the second work function layer extends along a second opposing sidewall of the third fin and along a second portion of the third upper surface of the third fin, wherein a first sidewall of the first work function layer is over the third upper surface of the third fin and contacts a second sidewall of the second work function layer, wherein a first upper surface of the first work function layer distal from the substrate is free of the second work function layer, and a second upper surface of the second work function layer distal from the substrate is free of the first work function layer, wherein the first work function layer and the second work function layer comprise different materials;
• and
• filling the recess with a gate electrode material.